SU1308929A1 - Digital spectrum analyzer - Google Patents

Abstract

The invention relates to a measurement technique and can be used to analyze the spectra of signals in real time. The purpose of the invention is to improve the accuracy of determining the frequencies of the components of the signal spectrum by jointly processing the phase spectra and calculating the deviations of the frequencies of the components from the corresponding discrete frequencies. The device contains analog-to-digital converter 1, multiplication blocks 2, 4 and 13, digital harmonic function generator 3, adders 5, 8 and 15, memory blocks 6, 7, 10, 11, phase calculation unit 9, coefficient setting unit 12, coefficient setting unit 12, subtraction unit 14, counters 16 And 19, decoder 17, clock generator 18, delay elements 20 and 21, And elements 22 and 23. The device provides a significant increase in the measurements performed compared to the prototype. 2 IL. S (L &: O eo x to x

Description

11308929

This invention relates to measurable. technology and is designed to analyze the spectra of signals in real time.

The purpose of the invention is to improve the accuracy of determining the frequencies of the components of the signal spectrum by jointly processing the phase spectra of contiguous signal realizations and calculating

2

blocks 6 and 7 of memory, respectively, and with output buses 25 and 26 of the device. The output buses of the adders 5 and 8 are connected respectively to the information inputs of the memory blocks 6 and 7 and the first and second inputs of the phase calculation block 9, the output of which is connected to the information input bus of the memory block 10, the output of the last

frequency deviations of 1 × 1X from co fO are the same as the information input of the corresponding discrete frequencies. , Figure 1 shows a block diagram of a digital spectrum analyzer; 2 shows timing diagrams for his work.

The analyzer contains an analog-to-digital converter (ADP) 1, the first multiplying unit 2, a digital generator

3harmonic functions, second .block

4 multiplications, the first adder 5, the first and second blocks 6 and 7 of the memory, the second adder 8, the block 9 calculating the phases, the third and fourth blocks 10 and

11 memory, block 12 setting the 1 / 2P coefficient, third block 13 multiplying, block 14 subtracting, third adder 15 first counter 16, decoder 17, Tat generator 18, second counter 19, first and second elements 20 and 21: delays, first and the second elements are And 22 and 23.

The signal input of the ADC 1 is connected to the input terminal 24 of the device, such as the input to the output of the second counter 19 and the input of the first counter 16 and the output bus of the ADC to the first inputs of blocks 2 and 4 multiplications, the second inputs of which are connected to the output cosine and sine buses respectively, a digital oscillator 3 of harmonic functions, the information input of which is connected to the output bus of the counter 16 and the input bus of the decoder 17, the first output (fig 2) of which is connected to the read enable inputs of memory blocks 6 and 7, and the second output (fig 2) - with lane the inputs of the elements And 22 and 23. The output of the clock generator 18 is connected to the clock input of the digital generator 3 harmonic functions, the input of the delay element 20, the second input of the element And 23 and the input of the counter 19, the output bus of which is connected to the address inputs of blocks 6, 7, 10 and 11 memories and a second input of the adder 15, the output buses of blocks 2 and 4 of the multiplication are connected to the output buses

2

blocks 6 and 7 of memory, respectively, and with output buses 25 and 26 of the device. The output buses of the adders 5 and 8 are connected respectively to the information inputs of the memory blocks 6 and 7 and the first and second inputs of the phase calculation block 9, the output of which is connected to the information input bus of the memory block 10, the output of the last sleep of the memory block 11 and the bus being reduced subtraction unit 14, the bus of which is readable is connected to the output of the 1 1 1 memory block, and the output is. The first 5 input of the multiplication unit 13, the second input of which is connected to the output, the bus of the 12 setting unit of the 1 / 2P coefficient, the first input bus of the adder 15 is connected to the output of the multiplication unit 13, and the output bus to the output 27 of the analyzer. The output of the delay element 20 is connected to the recording inputs of the memory blocks 6 and 7 and through the delay element 21 to the second input of the AND element 22, the output of which is connected to the recording input of the memory block 10. The output of the element And 23 is connected to the input of the record block

five

0

0

ka 11 memory. I

The analyzer works in the following way.

The blocks of the known device provide the calculation of pairs of Fourier coefficients by processing the realization of a signal of duration Tp, which corresponds to a resolution of the frequency uf 1 / Tp. real-time signal implementations, ADC 1 converts the signal into a series of digital values generated from pulses from counter 19 (FIG. 2a). In this case, each implementation is represented by N discrete samples, the Nth sample for this implementation is zero for the next one. For each sampling period, the digital generator 3 sequentially generates m pairs of harmonic function values for all discrete frequencies. The order of changing the values of the harmonic functions during the processing of each sample is defined by the number of the reference K coming from counter 16. Each value of the code of the A / D converter 1 is sequentially multiplied in blocks 2 and 4 by mr matrices 5

0

five

i-th equivalent filter. Solving equation (2) with respect to the frequency of the component, given that

 Ol

 one

uf, finally get

ФF.

 (i +: ;-) & f. (five)

cosine and sine values, respectively, and the results are fed to adders 5 and 8, where they are added to the numbers read from memory blocks 6 and 7. According to the N-th count, it forms with a strobe whose length is equal to the sampling period (Fig.26), which prohibits the reading of information. In this case, at the outputs of blocks 6 and 7, zero codes are formed, the feedback circuit fO is broken, and the first ones for the new realization of the works are recorded in blocks 6 and 7 of the memory. The address inputs of these blocks receive the number of the discrete frequency i, which ensures a one-to-one correspondence with the 3 harmonic functions generated by the block. At the end of the strobe, the feedback Hbie closes, and a valid one is formed in the memory blocks and forms the imaginary Fourier coefficients for each (Fig. 2b), allowing it to pass through m frequencies, at the second output strobe. Their calculation is completed by processing an (N-l) -ro count.

Taking into account that the value of -uf is predefined and known with great accuracy, it is sufficient to determine the dimensionless frequency of the i-th component

F; 2 ir

R.

i + (6)

The recording of the phases of the spectral components in the memory unit 10 is performed during the (N-l) -ro sampling period. For this, the decoder 17

pulses of the clock generator 18 to the write input of the memory block 10. Similarly, in block 11 of the memory is produced

The phase calculation unit 9 produces the result when the real and imaginary Fourier coefficients arrive at its input from the outputs of adders 5 and 8. The phase of the i-th component of the spectrum is determined by the expression

(t) (Q; - COg,) -t, (1)

where is CO; - the angular frequency of the i-th harmonic. NIKI; COj) - the angular frequency nearest,

discretes; the initial phase of the i-th component.

The values of 9 (t) are inserted sequentially for successive implementations of the signal with a time shift Tp 1 / uf. Therefore, the phase difference of the i-th component of the spectrum for neighboring realizations is equal to

 (with; -CO, -), i (2)

uf -

Limit values; determined by the bandwidth of an equivalent

uf filter

uf

W.,; ± lr.f. (3)

,; ± 21 G NPa sets these values of Q to expression (2), find the limits of variation of the phase difference

L. t, (4)

whence it follows that the magnitude of the difference does not exceed f and has a sign corresponding to the sign of the frequency deviation of the i-th component from the average frequency

i-th equivalent filter. Solving equation (2) with respect to the frequency of the component, given that

It forms at the second exit the strobe of Fig. 2c), which allows the passage of

 Ol

 one

uf, finally get

ФF.

 (i +: ;-) & f. (five)

It forms at the second exit the strobe of Fig. 2c), allowing it to pass

Forms at the second exit strobe (figv), allowing the passage of

Taking into account that the value of -uf is predefined and known with great accuracy, it is sufficient to determine the dimensionless frequency of the i-th component

F; 2 ir

R.

i + (6)

Forms at the second exit strobe (figv), allowing the passage of

The recording of the phases of the spectral components in the memory unit 10 is performed during the (N-l) -ro sampling period. For this, the decoder 17

Forms at the second exit strobe (figv), allowing the passage of

pulses of the clock generator 18 to the write input of the memory block 10. Similarly, in block 11 of the memory is produced

overwriting information from memory block 10. The recording in memory blocks 6 and 7 is made with a delay, resulting in the delay in the formation of private sums at the memory input blocks. The recording of phase values in the memory unit 10 is made with a delay, taking into account the phase formation time at the output of the unit 9. The recording of information in the memory unit 11 is performed without delay.

For THIS, during the (N-l) -ro sampling period for each frequency-discrete phase values of the previous implementation, it is copied from the block

10c, block 11, then the value of the phase of this implementation is recorded in block 10. At the output of the subtraction unit 14, a phase difference is formed,. Blocks 12, 13 and 15 provide the calculation of the adjusted value of the dimensionless frequency of each harmonic in accordance with expression (6). The second input of the adder 15 receives the number of frequency samples i from the output of the counter 19. Coordination of the operation of all nodes of the device is achieved by simultaneously changing the addresses of blocks 6, 7, 10 and

11 in accordance with the number i of the frequency increments.

The effect of increasing the accuracy of determining the frequency can be estimated from the ratio of the error introduced by a known device to the error introduced by the proposed device.

bf uf;

27

tF;)

(7)

where iOdF) is an absolute value

phase difference measurement errors,

From the expression (7) it follows that the effect of increasing the accuracy of determining the frequencies of the components of the signal spectrum is determined by the reciprocal of the measurement error of the phase difference of the coherent spectrum for two adjacent signal realizations. For example, if this error is 3, the accuracy is higher.

)

more than 100 times. Thus, the proposed device provides a significant increase in the accuracy of determining the frequencies of the components of the signal spectrum.

Claims (1)

Formula from Gain A digital spectrum analyzer containing an analog-digital converter, the first and second blocks are multiply, the first and second memory blocks, a clock generator, the first and second counters, the signal input of the analog-digital converter being connected to the input terminal of the device, the clock input with output the first and the input of the second counters, and the output with the first input buses of the first and second multiplication units, the second input buses of which are connected respectively to the cosine outputs and, the sine of the digital harmonic function generator, t the act input of which is connected to the output of the clock generator and the input of the first counter, the first inputs of the first and second, adders are connected respectively to the output buses of the first and second multiplicators, the second inputs of these adders are connected to the output buses of the first and second memory blocks, respectively, and output the tires of the real and imaginary Fourier coefficients of the device, and the outputs of the adders - with information mi input buses of the first and second memory blocks, respectively, address5 YU 15 20 25 thirty III) the 1st inputs of the latter are connected to the output bus of the first counter, differing in that, in order to increase the accuracy of determining the frequencies of the components of the signal spectrum by jointly processing the phase spectra of contiguous realizations, a phase calculation unit is inserted into it. the third and fourth memory blocks, the subtraction unit, the third multiplication unit, the 1 / 2P coefficient setting unit, the third adder, the decoder, the first and second delay elements, the first and second And elements, the first and second inputs of the phase calculation unit are connected to the output buses of the first and the second adders, respectively, and the output with the input information bus of the third memory block, the output bus of which is connected to the information input of the fourth memory block and the input of the decremented subtractor, the input of which is connected to the output bus h the fourth memory block, and the output with the first input bus of the third multiplication unit, the second input bus of which is connected to the output of the 1 / 2P coefficient setting unit, and the output bus to the first input of the third adder, the output of which is connected to the output bus of the device frequency codes, and the second input - with the address inputs of the third and fourth memory blocks and with the output bus of the first counter; the input of the decoder is connected to the read permission inputs of the first and second memory blocks, and its second output - with the first inputs of the first and second ele And, the clock generator output is connected to the second input of the second And element and the input of the first delay element, the output of which is connected to the recording inputs of the first and second memory blocks and through the delay element to the second input of the first And element, the output of which is connected to the recording input the third memory block, the output of the second element And is connected to the recording input of the fourth memory block. 50 FIG. Z Editor O. Yurkovetska Compiled by V. Velichkin Tehred A. Kravchuk Proofreader S. Cherni Order 1793/36 Circulation 731 Subscription VNSHPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk iab, d, 4/5 Production and printing company, Uzhgorod, st. Project, 4