SU1295450A1 - Device for delaying signals - Google Patents

Abstract

The invention relates to computing, in particular, to devices for delaying discrete signals, and can be used in the construction of synchronization units of computing devices. The aim of the invention is to expand the field of application of the device by obtaining several delay values in a single time interval. This goal is achieved by introducing into the known device a group of switches and a delay tag generator consisting of a switch and a second counter. The introduced blocks serve to establish both the number of different delays in each time interval and the values of these delays. 2 Il.

Description

The invention relates to computing, in particular, to devices for delaying discrete signals, and can be used in the construction of synchronization (of their blocks of computing devices).

The aim of the invention is to expand the field of application of the device by obtaining several delay values in one time interval,

FIG. 1 is a block diagram of a device for delaying signals; FIG. 2 - time diagrams

we who are working on the device.

The device for delaying signals contains a source of I clock pulses, a drive 2, a subtractor 3, a first counter 4, a driver 5 delays, a D-flip-flop 6, a group of switches 7, a switch 8 and a second counter 9. This also denotes outputs 0 of drive 2, the first 1 b, the second 12, the third 13 and the fourth 14 outputs and the group of outputs 15 of the source. 1 sync pulses, the first 16 and second 17 groups of inputs of the subtractor 3, inputs 18 of drive 2, device 19 degrading inputs 19, C inputs 20 of D triggers 6 and inputs 21 defining the value of the delay step.

FIG. 2 shows diagrams of signals at various points of the device: 01 - at the input of the device; S at the third output of the source 1 clock, & - at the outputs of the first counter 4; 2 - at the fourth output of the source 1 clock pulses; J - at the outputs of the second counter 9; S - at the outputs of the switch 8; ; to - at the outputs of the subtractor 3; J- - at the first output of the source 1 clock pulses; U - at the second output of the source 1 sync pulses; k - on the lane

your output of drive 2; l, m, n - on the group of the output of the source 1 sync pulses; o, p - at the outputs of the switch group 7; c - at the output of the first D-flip-flop; m - at the second output of drive 2; and - at the output - the second D-flip-flop; wed - at the third output of drive 2; h - output (K-l) -ro D-flip-flop; C - at the K output of the drive.

The device works as follows.

At each time interval (the time interval corresponds to the time interval from to and. T, o on

five

0

0

FIG. 2) the source 1 of the clock pulses at its third output 13 clock pulses (Fig. 2) having a repetition period equal to the time interval received at the counting input of the first counter 4. The last number is set at the outputs of the latter, for example A (Fig. 2 b , from t to t,). At the next time interval after the arrival of the next pulse, the next number A + 1 is set to the counting input of the first counter 4 (time point), and so on.

The pulses from the third output 13 of the source 1 clock pulses also arrive at the input of the initial installation of the second counter 9 and set its number O at the outputs (Fig. 2, t). Then, the pulses arriving at the counting input of the second counter 9 from the fourth output 14 of the source 1 of the clock pulses (Fig. 2d) are set at the outputs of the second counter 9 sequentially of the number l, 2 ..., in (Fig. 2y). After that, the second counter 9 comes next (its initial setup pulse (Fig. 25, t,) and sets it to zero, etc. Thus, at each time interval, the O number is set first on the outputs of the second counter 9 (Fig. 2a, -t), then the number 1 (), numbers -0

lo

2 () and so on to m (on

FIG. 2a is shown as an example the case when the second counter counts up to the number 4). These numbers from the outputs of the second counter 9 are fed to the control inputs of the switch 8.

Accordingly, the outputs of the switch 8 (which are the outputs of the imaging unit 5 (delay increments) on each time interval receive a signal from zero

the inputs 21d of the switch 8 (), the signal from the first inputs 21 of the switch 8), and so on to the mx inputs 21 of the switch 8 (the inputs of the switch are the inputs of the device delay delay values).

If the zero inputs 21 of the switch 8 apply the number D, the first inputs 21, - U, and so on until (t -1) -x

the inputs to which to submit, and to the inputs of the 21 inputs, apply zero, then at the outputs of the switch 8 (i.e., at the outputs of the driver, there are 5 delay steps) at each time interval

figs 2e. The number of words of a clapper 2 is stunted, where p is any positive integer (-.) In this case, upon transition

WCJKC

signal at the output of the subtractor 3 in the zero zero readout of information. occurs without gaps. Bit Subtractor 3, Counter 4 and Switch

8 are equal to p. I

The signal from the outputs of the first counter 4 is fed to the first group of 16 inputs of the subtractor 3, and the signal from the outputs of the time delay forming device 5 enters the second group 17 of the input of the subtractor 3. The signal at the outputs of the subtractor 3 arriving at the address inputs of the accumulator 1 looks as follows in FIG. 2g

The write pulse from the first output 11 of the source 1 clock pulses to the recording input of drive 2 (FIG. 2d) at a time when a signal is received at its address inputs equal to the signal at the output of the first counter (t, e, at tg-t,) . Thus, the signal, the arrival of r; s to input 18, accumulator 2 on the considered nth time interval (FIG. 2a), is recorded in the first

bit of drive 2 at address A (the signal that came in (n + 1) -th time interval - at address A + 1 and so on). The read pulses from the second output 12 of the source 1, the sync pulse arrive at the read input of accumulator 2 at the time when the signals A – b | ,,,. , A - ((fig, 2i), t, that is, on the nth time interval at output 10, accumulator 2, during tj-tj, a signal arrives at the input of the device in (p – yd) -th time interval , during - on (p-L)) - m time interval, etc. (fig, 2k, on the interval C – t, o conditionally shows the signal recorded in the first bit of accumulator 2 in the nth time interval at address A). Thus, at the output 10 of accumulator 2, a signal with a delay d is received at the same time interval, a signal with a delay U ,,, .., with a delay i.,, Setting at the inputs 21 tasks of the delay

T. I

neither the value of the value Lp, U ,, ..., l „. ,, it is possible to obtain any set of delays (the values of the delays in ticks should not exceed the capacity of the first counter

35 40 45

0

which can be obtained on the same time interval, is determined by the ratio of the duration of the time from the interval and the speed of the circuits implementing the proposed device. Usually 1 .1. - T / TQ-I, where T is the duration of the time interval, T is the period of access to the drive, Number of outputs in group 15 sources. ka 1 sync pulses is m - the number of reads from the accumulator during one time interval.

Depending on the signal supplied to the control inputs 19, the device, the output of the switch 7, a pulse passes from one of its inputs, From the output of the switch 7, the pulse goes to the C input of the first

20 D-flip-flop 6,.

Suppose, for example, that the first control input 19 of the device receives such a code that the C input of the D flip-flop 6 receives a 25 pulse from the input 5 of the clock source (Fig. 2o). Then the signal from output 10, accumulator 2 in the interval, i.e. on the interval when at 10, accumulator 1, the signal recorded in the first discharge of accumulator 2 is located on the (p – L |) th time interval (FIG. 2c), i.e., at input 18 of accumulator 2, the signal is delayed relative to the signal at the device input to U, time intervals, i

The delay in the second discharge of accumulator 2 relative to input 18 is on. The lock 2 is organized in the same way as in the first category. The signal from input 18 of accumulator 2 is recorded in the second bit of accumulator 2 by a write pulse in the interval t.-t, ((Fig. 2d), and the signal at output 10 of accumulator 2 is read out by read pulses (Fig. 2 (,). Signal output 10 of drive 2 is delayed relative to input 18, on D.

about

U „., Time intervals, and with respect to the input of the device on L, + Ld, U, U I ,,,., U, + y., Time intervals, i.e. in the nth time interval at the output 1Oj of accumulator 2 at time t, -t, a signal appears arriving at the input of the device in the (n – d, dd) -th time interval, at the time signal indicating to the input of the device on the (nth, th,) - m time interval, etc. (fig, 2t, in

time, p conditionally shows the signal recorded in the second bit of accumulator 2 at the time interval, at address A).

If the second control input 19, the device receives, for example, a measure such a signal that the C-input B-flip-flop 82 receives a pulse from the input 15f of the clock source (FIG. 2 and), then the input 18 of the accumulator 2 is delayed with respect to the input of the device on d ,, + l time intervals (fig. 2c). This signal is recorded in the third bit of accumulator 2 by a write pulse (fig. 2g), and the signal at the output 10 of accumulator 2 is read by read pulses (fig. 2i ). At output 10 of accumulator 2, the signal is delayed relative to the input of the device to U, + Lo + th „, U, + D (, + th„, u, + ug + D,.. „, U, + Do + D, time intervals3 t , e, on the nth cycle of an incident on output 10, accumulator 2

in time . a signal appears, arriving at the input of the device at (, -to,) - the m time interval, at the time - a signal, sending it to the input of the device at (n-U, -th,), the time interval, etc. (in Fig. 2 m at the time of to-t, g conditionally shows the signal recorded in the third bit of the accumulator. 2 in the nth time interval at address A) „

In the same way, the delay in other bits of the accumulator is carried out. So, for example, if the C input of the iD-flip-flop is 6 q., A pulse arrives from the input 5 of the clock source (Fig. 2p) 5, then a signal arrives at the input 18 of the storage device 2, shown in FIG. 2x. This signal is recorded in the K th bit of the accumulator by a write pulse. The sigpal at output l (the main accumulator in the nth time interval has the form shown in Fig. 2c (at the time, the signal recorded in the Kth bit of accumulator 2 is shown conventionally in the nth time interval at address A),

Thus, the signal recorded in the first bit of accumulator 2 in the nth time interval at address A appears at output 10. at the time t -, - t, at (n + ao) -th time interval

12954506

at the time of the (n + th,) - th time interval, and so on, at the output of lOj at the time t, –t at the (n + D, + + yd) th time interval, at the time of 5 m at (n + u, + u,) - M time interval and t, d.

Claims (1)

Invention Formula A device for delaying signals, containing a source of clock pulses, a drive whose outputs are the outputs of the device, and the write and read inputs are connected respectively, the first and second outputs of the source of clock pulses, the subtractor, the outputs of which are connected to address inputs. The accumulator, the first counter, the counting input of which is connected to the third output of the source of clock pulses, and the outputs are connected to the first group of inputs of the reader, K-1 D-flip-flops (K - the number of device outputs, 1 6 K L, L - the maximum number of delay intervals), with the D-inputs of the triggering trigger being connected to the corresponding outputs of the accumulator, the first information input of which is the device input, and input, K, is connected to the output of (il) -ro D-flip-flop, characterized in that, in order to expand the field of application of the device by obtaining several delay values in one time interval, a group of switches is entered into it, the control inputs which are the control inputs of the device delay, the information inputs are connected to the group of outputs of the clock source, and the outputs are connected to the C-inputs of the corresponding D-flip-flops, and the delay step driver, which consists of a second counter and switch, cat outputs connected to the second group of inputs of the subtractor, the counting input and the initial setup input of the second counter are connected respectively to the fourth and third outputs of the clock source, and the outputs to the control inputs of the switch, the information inputs of which are the device’s delay , VshkoZ 21t t, ti tftj, tfti tgtf ia R . . . A Ti I I 11 I Uffil .WttdC, JL I i fl, -i. yAGY1SGEG UFShch l i p t I t Ii I I and I till lit J t M; t (I 1 I Ml I I f I I 1 I I I. i GP P g -AJ M III i i I bkirik- - u KU, il8 LHM - ". g - “-“ - ““ iWie i, a, --- b,,.-.- j-i, I n t Ш ft ni-w ipchl, I jT i I I { ffil tdC, JL i-tf-tchl, M Jlji | ||. I I I I -AJ tft, tfti tft, If VNIIPI 622/58 Random polygons pr-tie, Uzhgorod, st. Project, 4 (3 ife .g Tirac 590 Subscription