SU1288655A1 - Sampled-data-regulator of water level in channel - Google Patents

Description

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The invention relates to the automatic regulation of objects with large capacities or distributed parameters in different industrial areas and can be used to automatically adjust the level of water on open canals.

The purpose of the invention is to improve the quality of regulation.

The drawing shows the structural hema of the proposed controller.

The channel channel level regulator contains memory block 1, first comparison block 2, adders 3 and 4, setting units 5 and 6, respectively, of the upper and lower quantization levels, second 7 and third 8 comparison units, division block 9, setting time setting 10, the element OR 11, the adder 12, the key 13, the pulse-width pulse modulator 14 and the integrator 15.

The device works as follows .25

At the beginning of each adjustment cycle, according to the setpoint 10 signal, the current value of the input signal X from the output of the level sensor (not noxasaHJ is stored in memory block 1. The fixed value of the X signal goes to totalizers 3 and 4. In totalizer 3, this signal is added to setpoint 5 signal , and in adder 4, the signal set by setter 6 is subtracted. The resulting signals are fed to the inputs of blocks 7 and B, respectively, to the other inputs of which the current value of the input signal arrives. When the current value of the input signal changes by more than the signal of the setting device 6 when increasing (or decreasing by an amount greater than the signal of the setting device 7 when decreasing), then a logical 1 will be generated at the output of the corresponding block 7 or 8, which through the OR 11 element will open the key 13. At the same time, the pulse-width modulator 13 forms an actuator (not shown) acting through the integrator 15, a regulating pulse, the duration of which is determined by the output signal of the adder 12. The polarity of this pulse determines the direction of movement of the actuator.

If during the adjustment cycle defined by setpoint 10, of 30

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five

If the input signal does not exceed the upper or lower quantization level, then the output of block 10 generates a cycle end signal, which the OR I1 element opens the key 13. This causes the output signal to be generated by the pulse-width modulator 14. At the same time the value of the input signal stored in memory block 1 is compared by block 2 with the current value of the input signal. The difference of these signals dX from the output of block 2 enters the input of block 9, where division is made by the amount of time t passed from the beginning of the control cycle and coming from setpoint 10. The result of the division characterizes the rate of change of the output signal during time t, i.e. characterizes the rate of change of water level in the channel. At the output of the adder 12 is formed

signal

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to 1-,

0

five

0

five

0

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where Xd is the level setting signal (KB shown),

K - scale factor. The value of the output signal of the block 12 through the key 13 sets the duration of the control pulse. The period for which the control pulses follow at low rates of change of the channel water level is determined by the selected duration T of the control cycle, and for large disturbances, by the time of deviation of the input signal from the output of the level sensor from the specified quantization level.

After each regulating action of the pulse-width modulator 14, a signal is given to the block 10 to proceed to a new adjustment cycle.

The invention makes it possible to increase the speed and stability of a pulse level regulator of water in a channel and thereby improve the quality of regulation. At the same time, the number of inclusions of the actuator is reduced, which also increases the reliability of the hydraulic structure and reduces operating costs.

Claims (1)

Invention Formula A pulse level regulator of water in the channel, containing three comparison units, a memory unit connected by an output to the first input of the first comparison unit, a level indicator, a first adder, a quantization upper level indicator, connected by an output to the first input of the first adder, a second adder, a controller a lower quantization level, connected by an output to the first input of the second adder, a time interval master and a series-connected key, a pulse-width modulator and an integrator, the second input of which is connected to the first the key input, and the output is the controller output, characterized in that, in order to improve the quality of regulation by increasing the speed and stability of the controller, a third adder connected by the output to the first input of the key is entered into it, and level block divider. connected Compiled by V.Pr. Mitsyn Editor A.Shandor Tekhred V..Kadar Proofreader I.Erdeyi Order 7805/45 Circulation 885 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 fO 15 20 25 the first input to the output of the first comparison unit, and the output to the second input of the third adder and the OR element connected by the output to the second input of the key, and the first, second and third inputs to the outputs of the second comparison unit, the third comparison unit and the first output of the setter, respectively time intervals, which are connected by the input with the second output of the pulse-width modulator, and the second and third outputs, respectively, with the first input of the memory unit and the second input of the division unit, with the second inputs of the first and second adders in connected to the output of the memory unit, the output of the first adder is connected to the first input of the second comparator unit, the output of the second adder is connected to the first input of the third comparator unit and the third input of the third adder and the second inputs of the first, second and third comparison unit and the memory block These are combined and are the input of the controller.