SU1283842A2 - Control device for motor - Google Patents

Abstract

The invention relates to the accumulation of information and makes it possible to increase the reliability of the device. If the voltage at the output of the integrator 22 exceeds the voltage of the source 26 of the reference voltage, then the comparison unit 23 generates the level of the logical unit, causing the switch 21 to operate, connecting the common power wire 8 to the control unit 9. If the level of logical unit comes from the control unit 9 to certain elements of the circuit, the device is put into stop, underwind and rewind and rewind mode. The invention is additional to the main auth.St. № 1185390. 2 Il.

Description

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The invention relates to

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the accumulation of information, namely to you engine management.

The aim of the invention is to increase the reliability of the engine control device.

Fig. 1 is a diagram of one of the variants of the proposed motor control device; figure 2 - the device frequency limiter.

The device contains a control transistor 3, limiting resistor 2, a direct current motor 3, a switching voltage divider 4, the first and second inputs of which are connected to the positive power supply bus 5 via the first and second switches, respectively; 6 and 7, and a common power wire 8. The control unit, the inputs of the first and second switches 6 and 7, is connected to the outputs of the control unit 9, made in the form of a driver for switching on the operating modes. The output of the switched divider 4 is connected to the base of the parasitic one with the base of the control transistor 1.

The device also contains an additional control transistor 10. an additional limiting resistor 11, the first and second bias resistors 12 and 13, the first and second diodes 14 and 15, the first additional switch 16 and the additional commutator voltage divider 17. The collectors of the control transistor 1 and the additional control transistor 1 O are connected respectively to the positive power supply bus 5 and to the negative power supply bus 18, respectively, through the limiting resistor 2 to the additional limiting resistor 1 1. The DC motor 3 is connected to a common connection point between the emitters of the control transistor I and the additional control transistor 10 and the first terminals of the first and second bias resistors 2 and 13 and the common wire 8 of the power supply. The second I and I of the first and second bias resistors 12 and 13 are connected respectively to the bases of the control transistor I and the additional control transistor 10. The input of the additional switched divider 17 of the reference voltage is connected to the negative bus 18 of the power supply circuit.

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it through the first additional switch 16, the control input of which is connected to the base of the additional control transistor 10. The switching voltage divider 4 and the additional switching voltage switch 17 are connected to the common power supply wire 8, respectively, through the first and second diodes 14 and 15. Moreover, the cathode of the first diode 14 and the anode of the second diode 15 are connected to the common power supply wire 8.

The device contains, in addition, an integrator 19 connected by the power bus 5 and the common power cable 8, I1Sh 20, the first input of which is connected to the control unit 9, the second and third additional switches 21 and 22, the unit

23, a frequency limiter 24, a pulse shaper 25, an additional source 26 of the reference ground voltage, and first and second capacitors 27 and 28, connected by first terminals to the collectors of the control transistor I and the additional control transistor, respectively. The second conclusions of the first and

 the second capacitors 27 and 28 are connected via the pulse shaper 25 to the first input 29 of the limiter

24 frequencies connected by output 30 to the second input of the OR element and

5 connected by a second input 31 to one of the outputs of control unit 9 connected by a reset input via a second additional switch 21 with a common power supply wire B connected via a third additional switch 3 to the output of the integrator 19 connected to the first input of the comparator unit 23. The second input of the comparator unit 23 is connected to the output of an additional source 26 of the reference voltage. The output of the comparator unit 23 is connected to the control input of the second additional switch 21. The control input of the third additional switch 22 is connected to the output of the OR element 20.

Frequency limiter 24 consists of the third and fourth capacitors S ditch 32 and 33, connected by the first leads to the second input of the element OR 20, from the third diode 34 and the resistop 355 connected by the first high

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water from one of the outputs of the control block 9. The second terminal of the third capacitor 32 is connected to the output of the pulse driver 25, connected to the first terminal of the third diode 34, The second terminal of the third diode 34 is connected to the second terminals of the fourth capacitor 33 and resistor 35. At the same time, the first terminals; the third and fourth capacitors 32 and 33 coincide with the output 30 of the limiter 24 frequency, and the first output of the resistor 35 - with the second input 3, the Second output of the third capacitor 32 and the first output of the third diode 34 coincide with the first input 29 of the limiter 24 frequency.

The motor control device operates as follows.

If the voltage at the output of the integrator 22 exceeds the voltage of the additional source 26 of the reference voltage, then the comparison unit 23 generates a logical unit level that triggers the operation of the second additional switch 21 connecting the common power wire 8 to the control unit 9. The control unit 9 generates a logic zero level at the control inputs of the first and second switches 6 and 7 and the first and additional switches 6 and 22, which ensures the locking of the control transistor 1 and the additional control transistor 10 and the absence of voltage on the DC motor 3 . The latter puts the device into stop mode.

If from block 9 control 1 to the element OR 20 enters the level of a logical unit, then the third additional switch 22 triggers, connecting the common power supply wire 8 to the output of the integra-- tion. torus 19. In this case, the comparison unit 23 generates a logic zero level, closing the second additional switch 21, which ensures the blocking of the activation of operation modes. At the same time, the logic level, the units from the control unit 9, causes the operation of the frequency limiter 24 and the first switch 6, which opens the control transistor through a switched one. divider 4 support voltage. At the same time the engine 3 direct current

838424

It is set in the loop selection mode, Impulse, produced by the DC motor 3, from the control transistor collector. Step 1 and through the first capacitor 7, the driver of the 25 pulses, the frequency limiter 24 and the OR element 20 are fed to the control input of the third additional switch 22.

JO As a result, at the output of the comparator unit 23, a logic zero level is maintained, which ensures the locking of the winding mode.

If the level of logical units

15 from the control unit 9 to the control input of the second switch 7, the latter is activated. In this case, the second switch 7 opens the control transistor 1 through a commutator divider 4 of the reference voltage, providing the installation of the DC motor 3 in the forward winding mode. The pulses produced by the DC motor 3 are removed from the collector of the control transistor 1 and fed through the first capacitor 27, the driver of 25 pulses, the limiter 24 frequency

30 and the OR element 20 to the control input of the third additional switch 22. The latter leads to the fact that the output of the comparison unit 23 maintains a logic zero level,

35 blocking forward mode.

If from the control unit 9 the level of the logical unit arrives at the equalization input of the first additional switch 16, then the latter is triggered. In this case, the first additional switch 16 through an additional switched

45, the reference voltage divider 17 opens an additional control transistor 10, allowing the installation of the DC motor 3 in the rewind mode. Impulses

0 driven by the DC motor 3, are removed from the collector of the additional control transistor 10 and fed through the second capacitor 28, the driver 25 and 5 pulses, the limiter 24 frequencies and the OR element 20 to the control input of the third additional switch 22. As a result, the output

Comparison unit 23 maintains a logical zero level, which provides blocking of the rewind mode.

Claims (1)

Invention Formula Engine control device auth.St. No. 1185390, characterized in that, in order to increase the reliability of the motor control device, an integrator connected between a positive power bus and a common power wire, an OR element, the first input of which is connected to a control unit made in the form of an operating mode driver , the first and second capacitors connected by the first terminals to the collectors of the control transistor and the additional control trazistor, respectively, the second and third additional switches, block comparison, frequency limiter, pulse shaper and an additional voltage source, the second terminals of the first and second capacitors are connected via a pulse shaper to the first input of a frequency limiter connected by the output to the second input of the OR element and connected to the second an input to one of the outputs of a control unit connected by a reset input through a second auxiliary switch with a common power wire connected through a third auxiliary switch to an integrator output connected to the first input of a comparison unit that is connected by a second input to the output of an auxiliary reference voltage source and connected to the output with the control input of the second auxiliary switch, and the control input of the third auxiliary switch is connected to output element OR. 3 // I Fiz.g.