SU1282324A1 - Meter of characteristics of analog-to-digital converters - Google Patents

Abstract

The invention relates to the field of instrumentation technology and is intended for experimental research, process and output control of analog-to-digital converters and digital voltmeters. The invention allows to expand the functionality of a device comprising a counter 4, two reversible counters 6 and 7, a source 1 of exemplary voltage, a voltage summation unit 2, a digital-to-analog converter 3, a pulse generator 5, the first block 8 of code comparison, due to introducing into the device the second 9 and third 10 blocks of comparison of codes, adder 11, first 13 and second 12 switches, arithmetic unit 14. 1 c.p. f-ly, 3 ill.

Description

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The invention relates to instrumentation engineering and is intended for experimental studies of process and output control of analog-to-digital converters (ADC) and digital voltmeters (CB).

The purpose of the invention is to expand the functionality by additionally determining the size of the real quantum size, differential nonlinearity, and shifting the quantization levels.

FIG. 1 shows the functional scheme of the proposed meter; in fig. 2 is a diagram explaining the principle of its operation; in fig. 3 - the example of the implementation of the arithmetic unit

The ADC characteristic meter contains a source of 1 model. For example, Mon, voltage summation unit 2, digital-to-analog converter (DAC) 3, counter 4, generator of 5 pulses, reversible counters 6 and 7, blocks 8-10 of code comparison, adder 11, switches 12 and 13, the arithmetic unit 14, the first output bus 15, the second output bus 16 and the input bus 17, controlled by the ADC 18.

Arithmetic unit 14 (Fig. 3)

four

It contains the first 19 and second 20 blocks of inverters, the first 21, the fifth 22, the third 23, the second 24 and the fourth 25 adders.

FIG. Figure 2 shows the plot of the scale of the controlled converter 18, where the following terms are taken:

5c - input value (voltage)

ADC 18;

h is the output code of the ADC 18; a is the reference code corresponding to the scale point of the A / D converter 18, near which the characteristics are measured; the dependence of the probability of the appearance of a certain code on the voltage at the input of the ADC 18; nominal frequency of the ADC quantum 18; .

the nominal value of the level corresponding to the center, and q (a-0.5) and q (a + 0.5) - to the boundaries of the a-th quaita; ty - the real average value of the center, and t - and the boundaries of the a-th quantum of the ADC 18.

P, (x)

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Before the start of control, the corresponding pins of the A / D converter 18 are combined with buses 15-17, and from the output of source 1 to the input of controlled converter 18 an exemplary voltage U |, is applied, pulses from the output of generator 5 pulses do not arrive. The counters 4, 6, and 7 are set to zero state on the reset circuits, not essential for explaining the operating principle of the proposed meter and, therefore, not shown in FIG. 1. The reference inputs a and Q are supplied to the corresponding inputs of block 8 and the arithmetic block 14. Since the proposed meter works in the following mode, the start of the control is not determined with respect to the moment of estimation.

In the operating mode, the generator 5 generates a pulse sequence, the duty cycle of which depends on the ratio of the conversion times of the DAC 3 and the A / D converter 18. On the leading edge of the pulses generated by the pulse generator 5, a variable code N is formed in the counter 4, converted by the DAC 3 into a scanning auxiliary effect, span which exceeds the span of the total error of the ADC 18.

On the trailing edge of this pulse, the ADC 18 is launched. At the end of the conversion process in ADC 18, block 8 analyzes the ratio of the codes h and a. °.

The meter consists of two independent channels, similar in construction, differing in the control signals arriving at them from block 8.

Each channel represents a tracking system containing a local feedback circuit. Consider the work of one of the channels (first). Block 9 controls the switch 12

IMC in the way that when N .N

Speech is subtractive, and when N .N, underIj 1 oD X

confirmation h and goes to the summing input.

Thus, at the output of the latter, a code is formed, at which the occurrence of outcomes is h-4 a and h. and on the corresponding outputs of the switch 12 during some periods of the launch of the ADC 18 evenly. This code is

estimating the actual quantization level between a and +1 quanta relative to the nominal center of the a-th quantum

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Vr N (-h „-) Algorithm of the first channel opik

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Similarly, for the second channel

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Equilibrium in the second channel occurs at

z (h, a) .Y (N.N;;: ;;

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Considering that

.. - code corresponding to the nominal size of the ADC quantum 18, you can

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based on the estimates obtained by the moves of the reversible counters 6 and

block 14 performs the calculation of christik ACGT 18:

the displacement of the total error (the real center of the a-th quantum

. “Rech7, ° NjiU iNjlMX;

real size a-th quantum

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differential nonlinearity

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quantization level offsets

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Thus, an Aimp1 meter offers the characteristics of an ADC that allows you to continuously monitor several characteristics of an A / D converter (defined in parallel). This is achieved due to the possibility of independent and simultaneous determination of the displacements of two adjacent real quantization levels relative to the nominal value or center of the monitored quantum.

Claims (2)

1. An analog-to-digital converter characteristics meter that contains a counter, two reverse meters, an exemplary voltage source, the code of which is connected to the first input of a voltage shunting unit, the second input of which is connected to the output of the digital-analog converter, and the output is the first output the meter bus, whose second output bus is the pulse generator output, the first inputs of the first code comparison unit are input wiring, and the second inputs are the first reference code bus, differing In order to expand functionality due to the additional determination of the quantum quantum size, differential nonlinearity and quantization level offset, the second and third code comparison blocks, an adder, two switches and an arithmetic unit, the first inputs of which are bus of the second reference code, and the first outputs are the third output bus and connected to the corresponding first inputs of the adder, the outputs of which are connected respectively to the inputs of the digital-analogue terminal transformer, and the second inputs I combined with the first inputs of the second and the third code comparison block and are connected to the counter outputs, the second inputs of the third code comparison block are combined with the second inputs of the arithmetic block and connected to the outputs of the first reversible counter, the first and second outputs of which are connected respectively to the first and second outputs of the first switch, the first input of which connected 5K .:: the third Olok Comparison of the third unit and the second and third input correspond to the first and second outputs of the first code comparison unit, the third and fourth outputs of which are connected to the first and second inputs of the second reversible counter via the second switch which are connected to the second inputs of the second code comparison unit and the third inputs of the arithmetic unit, the second, third, fourth and fifth outputs of which are the fourth, fifth, sixth and seventh output buses, respectively; a pulse generator output and the output of the second code comparing unit is connected to a third input of the second switch. 2. A device according to claim 1, characterized in that the arithmetic unit is made on five summers and two inverter blocks, the inputs of the first inverter block are combined with the first information inputs of the first and second adders and are the second inputs of the block, the first inputs of which are entrances And 8. 2 0 / 3 five f5 20 2 i6 the inverted block and the second; information inputs of the second adder, output 1 of the BTopoi o block of inverters are connected to the first information inputs of the third and fourth adders, the second information inputs of the last of which are the third inputs of the block, the control input combined with the control input of the third adder, the outputs of the fourth, second, and third suture are the fifth, fourth, and third outputs of the block, the second outputs of which are the outputs of the fifth adder connected to the second the first information inputs of the fifth adder are connected to the outputs of the first inverter unit, the second information inputs are combined with the second information inputs of the first adder and are the third inputs of the block, the control input of the fifth adder is | Bus of a logical unit, and the outputs of the first adder are the first outputs of the block. qfj-ia-0,5} q „a ,five) t but fi.3