SU1280606A1 - Device for analyzing and changing numeric fields - Google Patents

Abstract

The invention relates to the field of digital computing and can be used in the processing of structurally complex information (graphs, tables), analysis of the structures of algorithms and programs, optimization of linear sections of graph-schemes of algorithms. It allows you to perform a frequently encountered operation of analyzing and replacing numeric fields that encode a semantic representation of graphs. The purpose of the invention is to increase the speed of the device. The device contains two input registers, a mask generation unit, two mask registers, two groups of AND elements, a correction block, a group of OR elements, two inputs, two outputs. The mask forming unit contains two NOT elements, two groups of elements. And, -but elements AND, a group of elements OR, two comparison schemes. element OR. The correction block contains a group of elements OR, two groups of elements AND, an element NOT. Two data elements that need to be analyzed and replaced with numerical FIELDS, go to the input registers and from the output of the latter to the inputs of two groups of AND elements and to the inputs of the mask generation unit. With the help of the latter, the possibility of replacing numerical fields is analyzed in accordance with the rule of generalizing linear sections of HRF-schemes and the result of the analysis is presented at the second output of the block, which is the IO) second output of the device, and also forms masks at the first and third outputs of the block. The masks from these outputs go to the registers of the masks and from the outputs of the latter to the corresponding groups of elements I. From the output of the second group of elements I, the highlighted field is fed to the first input of the correction unit, to the second input of which a signal is received from the fourth output of the block that the first element The data has 1 or 2 inputs in the graph and the selected field from the vsGryy element, respectively, should not OR should be shifted to the size of one FIELD to the right. From the outputs of the first group of elements AND and the correction unit, the allocated fields are fed to the inputs of the group of elements OR, where they are combined and fed to the first output of the device. 5 il.

Description

This invention relates to digital

computing, and can be used in the processing of structurally complex information (graphs, tables), analysis of algorithms, programs.

In computing, the analysis of the possibility of replacing numeric fields and replacing numerical fields with a positive result of analysis is often used. For example, when analyzing programs and optimizing linear parts of algorithms, the operation of aggregating algorithmic actions is often encountered. Let an algorithmic action be represented by data elements of the following structure:

"From the Item:" Spole 3

 communication field; “I Field 3: 0 number; Communication field:. field 2. : field 1 field 0:

g: Field 0: 1 number 1 HI ... II; g Field 1: O number

I 1 number; - Field 2: 0 “number; -i Number: .000 .. .00, i | OOP. ..01, I, 000 ... 10.1 ... /

- (P-1

III ... 10. 25

40

n - (, 30

Thus, the data element field is a signed integer. Denote the jth field of the i-ro of the data element Pi and the value of the sign bit of this field - ZP,; , the value of the numeric bits of this gender is Mnifj ,. The condition for the possibility of replacing the numerical fields of the device for analyzing and replacing numerical fields is the truth of the hyphenation.

L () L "() A (P10 111 .... 111) V (() L (P10 111 (.v ... 111))) A () L (... 1.1) l

L (() V ()) L. ()

The replacement operation for the data elements P13 P1 2 P11 111 ... 11 and P23-P22 P21 111 ... 11 gives the result P13 P12 P21 111 ... 11, and for the data elements P13 P12 P11 P10 and P23 P21 111 ... 11 - the result of П13 П12 П11 П21.

The purpose of the inventions is to increase the device's activity.

FIG. 1 shows the functional- On the diagram of the analysis device and the replacement of numerical fields; in fig. 2 is a functional diagram of a mask generation unit; in fig. 3 - functional block correction circuit; in fig. 4 45

50

five

0 15

0

five

0

0

"

five

0

functional diagram of the group of elements OR; in fig. 5 - the functional diagram of the group of elements I.

The device contains the first 1 and second 2 input registers, the mask generation block 3, the first 4 and second 5 mask registers, the first 6 and second 7 groups of AND elements, correction block 8, the group of 9 elements OR the second element NOT 10, the second group 11 elements AND , the first and fourth elements And 12 and 13, the first group of 14 elements And, the second and third elements And 15 and 16, the first element NOT 17, the first element OR 18, a group of 19 IL elements, the second and first circuits 20 and 21 of the comparison, n element 22 and 22, the second element OR 23, a group of 24 elements OR, the first 25 and the second 26 groups of elements AND, el ment NOT 27.

The analysis device and the replacement of numeric fields (Fig. 1) operates as follows.

The first data element is entered into the first input register 1, the second data element is entered into the second input register 2. From the outputs of the first 1 and second 2 input registers, the first and second data elements arrive at the first 6 and second 7 groups of elements I. The inputs of the first 4 and second 5 mask mask registers are received from the first and third outputs of the mask generation unit 3, respectively. The corresponding bits (Fig. 1) of the fields of the corresponding data elements are received at the first and second inputs of the mask generation unit 3. Element AND 22 of the mask generation unit (Fig. 2) generates a sign of the possibility of replacing numeric fields, including the value of the element NOT 10, which represents the G12, the output value of the element OR 18, which represents the value (GF11 L (... 11) ) V (ЗП11Д А (П10 111 ... 11)), formed by the values of the outputs of the elements 15, 12 and 16, the output value of the coincidence of the second comparison circuit 20, which is the value of (VNP CH23) V (), formed with using the values of the outputs of the first 14 and second 11 groups of elements AND and the group of 19 elements OR, carrying out x the choice of the field c and the containing zeros in the PR, the output value of the coincidence of the first comparison circuit 21, which is the value (CP22 PR13), the discharge value n of the 2nd input of the block, which is P21, the output value of the And 13 element, representing the value (P20 111 ... 11). The direct and inverse outputs of the element OR 23 have constant values equivalent to zero and one, respectively, which establish the respective bits of the masks (Fig. 2). The output of the element NOT 17, which has the value ZP11, and the direct output of the element And 12, which has the value (P10 111 ... 11), set the corresponding bits (Fig. 2) of the first mask, the latter being the fourth output of the formation unit 3 masks and controls the groups of elements AND (FIG. 3) of the correction unit 8 that shifts the missing field of the second data element depending on the value (... 11) one field to the right. With the help of a group of 9 elements OR, a logical addition of the codes from the outputs of the elements AND of the first group 6 and the output of the correction block 8 is carried out. The result goes to the first output of the device, the second output of which is the direct output of the And 22 element (Fig. 2) J

Claims (1)

The invention relates to digital computing, and can be used in the processing of structurally complex information (graphs, tables), analysis of algorithms, programs. In computing, the analysis of the possibility of replacing numeric fields and replacing numeric fields with a positive result of analysis is often used. For example, when analyzing programs and optimizing linear parts of algorithms, the operation of aggregating algorithmic actions is often encountered. Let an algorithmic action be represented by data elements of the following structure: "C Data item:" Spole 3 communication fields; “I Field 3: 0 number; Communication field:. field 2. : field 1 field 0: g: Field 0: 1 number 1 HI ... II; г Field 1: О number I 1 number; - Field2 0 “number; -i Number: .000 .. .00, i | OOP. ..01, I, 000 ... 10.1 ... / - (P-1 III ... 10. 1 n- (, SO, the data element field is a signed integer. Denote by je the field The i-ro of the data element is the value of the sign bit of this field - GF ,;, the value of the number bits of this field is Mnifj. The condition for the possibility of replacing the numerical fields of the device for analyzing and replacing the number fields is the truth of the hyphenation L () L "() A ( P10 111 .... 111) V (() L (P10 11 ... 111))) A () L (... 1. L (() V ()) L. (). Replacement operation for elements data, P13 P1 2 P11 111 ... 11 and P23-P22. P21 111 ... 11 gives the result P13 P12 P21 111 ... 11, and for data elements P13 P12 P11 P1 0 and P23 P22 P21 111 .. 11 is the result of P13 P12 P11 P21.The purpose of the inventions is to increase the device’s performance.Figure 1 shows the functional diagram of the device for analyzing and replacing numeric fields; Fig. 3 is a functional block diagram of the correction; Fig. 4 is a functional block diagram of a group of elements OR; in fig. 5 is a functional diagram of a group of elements I. The device contains the first 1 and second 2 input registers, the mask generation unit 3, the first 4 and second 5 mask registers, the first 6 and second 7 groups of elements AND, the correction unit 8, group 9 elements OR the second element NOT 10, the second group 11 elements And, the first and fourth elements And 12 and 13, the first group 14 elements And the second and third elements And 15 and 16, the first element NOT 17, the first element OR 18, a group of 19 IL elements, the second and the first circuits 20 and 21 of comparison, the fifth element AND 22, the second element OR 23, a group of 24 elements AND And, the first 25 and second 26 group of AND gates, NOT element 27. The apparatus z.ameny analysis and numerical fields (FIG. 1) operates as follows. The first data element is entered into the first input register 1, the second data element is entered into the second input register 2. From the outputs of the first 1 and second 2 input registers, the first and second data elements arrive at the first 6 and second 7 groups of elements I. The inputs of the first 4 and second 5 mask mask registers are received from the first and third outputs of the mask generation unit 3, respectively. The corresponding bits (Fig. 1) of the fields of the corresponding data elements are received at the first and second inputs of the mask generation unit 3. Element AND 22 of the mask generation unit (Fig. 2) generates a sign of the possibility of replacing numeric fields, including the value of the element NOT 10, which represents the G12, the output value of the element OR 18, which represents the value (GF11 L (... 11) ) V (ЗП11Д А (П10 111 ... 11)), formed by the values of the outputs of the elements 15, 12 and 16, the output value of the coincidence of the second comparison circuit 20, which is the value of (VNP CH23) V (), formed with using the values of the outputs of the first 14 and second 11 groups of elements AND and the group of 19 elements OR, carrying out x the choice of the field c and containing zeros in the state of emergency, the output value of the coincidence of the first comparison circuit 21, which represents the value (CP22 PP13), the discharge value n of the 2nd input of the block, which is Z21, the output value of the And 13 element, value (П20 111 ... 11). The direct and inverse outputs of the element OR 23 have constant values equivalent respectively to zero and one, which set the corresponding bits of the masks (Fig. 2). The output of the element NOT 17, having the value of ЗП11, and the direct output of the element 12, having the value (P10 111 ... 11), set the corresponding bits (Fig. 2) of the first mask, the latter being the fourth output of the mask generation unit 3 and controls the groups of elements AND (FIG. 3) of the correction unit 8, which shifts the skipped field of the second data element depending on the value (... 11) one field to the right. With the help of a group of 9 elements OR, a logical addition of codes from the outputs of the elements AND of the first group 6 and the output of the correction block 8 is performed. The result goes to the first output of the device, the second output of which is the direct output of the AND 22 element (FIG. 2). J Formula of the Invention An analysis and replacement device for numeric fields containing two input registers, two mask registers, two groups of elements And, a group of elements OR, the outputs of the first and second input registers are connected bitwise to the first inputs of the elements of the first and second groups, respectively, and the outputs of the first and second mask registers are connected bitwise to the second inputs of the elements of the first and second groups with Respectively, the outputs of the elements AND of the first group are connected bitwise with the first inputs of the elements OR of the groups, the outputs of which form the first output of the device, characterized in that, in order to improve speed, it contains an additional unit for forming masks consisting of two elements NOT of two elements ШШ, five elements И, group of elements ШШ, two groups of elements И, two comparison circuits, and a correction unit consisting of element NOT, a group of elements OR, two groups of elements И, and the bits starting from zero to 2) th outs ln The first input register is connected bitwise with the first inputs of the elements of the first group of the mask generation unit (number of digits), bits, starting from zero to (n-1) -th outputs of the first input register, connected bitwise to the inputs of the first element and the mask generation unit, bits, starting from the nth to (2n-2) -th outputs of the first input register, are connected bitwise with the first inputs of the elements And the second group of the mask-forming unit, (2n-1) -th discharge of the first the input register is connected to the second inputs of the elements of the second group Lok forming the masks, with the input of the first element NOT the mask forming unit, with the first input of the second element AND the mask forming unit, with the first inverse input of the third element AND the mask forming unit, (Zn-1) th output of the first input register is connected to the input of the second element of the mask generation unit, bits, starting from the 3 rd through (4n-2) -th outputs of the first input register, are connected in series with the inputs of the first group of the first comparison circuit of the mask generation unit, the bit from zero to -1) -th output of the second input The first register is connected to the inputs of the fourth element AND the mask generation unit, bits, starting from the 2nd to the (3n-2) -th outputs of the second input register, connected bitwise to the inputs of the second group of the first comparison circuit of the mask generation unit, bits with Zn-th (4n-2) -th outputs of the second input register are connected bitwise to the inputs of the first group of the second comparison circuit of the mask generation unit, the outputs of the AND elements, the second group of the mask generation unit are connected to the first inputs of the OR elements of the mask generation unit, etc. my out The first element AND the mask generation unit is connected to the second input of the second element AND the mask generation unit, from the zero to (P1) th bits of the input of the first mask register, to the input of the NOT element of the correction unit, with the first inputs of the AND elements of the first group of the correction unit, the inverse output of the first element AND the mask generation unit is connected to the second input of the third element AND the mask generation unit and with the second inputs of the AND elements of the first group of the mask generation unit, the fluxes of which are connected bitwise to the second inputs in the OR group of the mask generation unit, the outputs of which are connected to the second group of inputs of the second comparison circuit of the mask generation unit, the outputs of the second and third elements AND the mask generation unit are connected to the first and second inputs of the first OR element of the mask generation unit, with the output of the second element of the formation unit masks, output of the first element OR of the mask generation unit, outputs Equal to the first and second comparison circuits of the mask generation unit, (2n-1) th output of the second input register, output of the fourth element And the mask generation unit is connected to the first, second, third, fourth, fifth and sixth inputs of the fifth element AND the mask generation unit, respectively; the output of the first element of the NOT mask generation unit is connected to the nth (2n-1) -th bits the input of the first mask register, the direct and inverse outputs of the fifth element AND the mask generation unit are connected respectively to the first and second inputs of the second OR element of the mask generation unit; the direct output of the second OR element of the mask generation unit is connected . from the 2nd to the (4n-1) th bits of the input of the first mask register and from the nth to (2n-1) th bits of the input of the second mask register, the inverse output of the second OR element of the mask generation unit is connected from zero to (n-1) th bits and 2 th to (4 n-1) th bits of the input of the second mask register, and the direct output of the fifth element And the mask generation unit is the second output of the device, from zero to ( n-1) -th bit of the outputs of the elements And the second group are connected bitwise with the first inputs of the elements OR of the group of the correction unit, from the n-th to (2n-1) -th discharge of the outputs And the second group of elements are connected in bit with the second inputs of the elements of the OR group of the correction unit, from the 2nth to (4p-1) th bits of the outputs of the elements AND the second group are connected to the second inputs of the corresponding elements of the OR group, the output of the element of the correction unit is connected with the first inputs of elements And the second group of the correction unit, the outputs of the elements of the group W of the correction unit group are connected to the second inputs of the elements AND of the first and second groups of the correction unit, bits from the zero to (n-1) th outputs of the elements And the second group of the correction unit are connected a second input of OR group, p ASP. From the 0th to (p-1) -th outputs of the Element5 And the first group of the correction unit, bitwise are connected to the second inputs from the nth to (2n-1) -th elements of the OR group. 1Nl