SU1280438A1 - Device for displaying information on television display - Google Patents

Abstract

The invention relates to automation, computing and television technology and can be used to display various graphic information on the screen of various television-type indicators. The purpose of the invention is to strengthen the device and expand the application area of the device due to the possibility of displaying images that are symmetrical with the main one. The introduction of three registers. 7, 13,

Description

The invention relates to automation, computing and television technology and can be used when displaying character-graphic information on the screens of various television-type indicators.

The purpose of the invention is to simplify the device and spread out the area of application of the device due to the possibility of displaying images that are symmetric to the base.

FIG. 1 is a functional diagram of the proposed device; FIG. 2 is a decomposition matrix of one of the symbols displayed on the TV indicator; in fig. 3 is an example of symbols having a symmetrical structure.

The device comprises a memory block 1, a generator of 2 symbols, a shift register 3, a video signal generation unit 4, a television indicator 5, a synchronization unit 6, a register 7, switches 8 and 9, a reading address counter 10, a switch 11, a 12-row counter, registers 13 and 14, shift register 15, switch 16.

The 2-character generator contains a register 17, ROM 18, a 19-line counter, synchronization unit 6 contains a clock generator 20, a horizontal sampling counter 21, a horizontal sweep function 22, a frequency divider 23, a clock generator 24, device 25-27.

The device works as follows.

The character codes displayed on the TV-indicator screen and the bits of the method for displaying them from the computer data bus (with -1 its bits) go to memory block 1, from where they read and arrive at the TV scanning frequency: character codes - in register 17, and the bits of the way they are mapped are in registers 13 and 14. From register 17, character codes go to a portion of the address inputs of ROM 18, which stores codes in the memory cells that exactly match the rows of the decomposition matrix of characters displayed on the screen. The rest of the address inputs of the storage device 18 receive the codes from the outputs of either a counter of 19 rows or a counter of 12 rows, which are connected via a switch 11, depending on the state of its address input to which

the control bit comes from register 13. In the aggregate, the bit from register 1 7 and the output bits of switch 11 constitute the complete cell address

memory ROM 18. Depending on the state of the register 17, on which the code of the address character is set and the number of the line damping pulse arriving at the inputs of the counter 19

rows, working on the summation, and the counter 12 lines, working on the subtraction from the ROM 18, is considered the corresponding row of the decomposition matrix of the character. And if the exit

the switch 11 will be connected to the 12-row counter operating on the subtraction, the rows of the decomposition matrix of the characters will be displayed on the TV screen of the indicator in the reverse order of their

the output, when the 19-line counter that is working on summation, connected to the output of the second switch 11, and the displayed characters will be displayed symmetrically relative to the vertical of the screen (Fig. 3a). Rows of the decomposition matrix of the characters to convert them from parallel code to serial, with the aim of their subsequent issuance at the input of the indicator

for display, it comes from the output of the ROM 18 to the inputs of the shift register 3 right 3 and the shift register 15 left, from which information in the serial code goes to

the inputs of the switch 16. The latter, depending on the bit arriving at its address input from the output of register 14, connects to the input of the indicator or the output of the register 3 shift

to the right, or exit register 15 shift left. Obviously, the symbols displayed on the screen of the indicator are displayed symmetrically about the horizontal axis (Fig. 36).

The codes of the characters displayed on the TV screen of the indicator, and the bits of the way they are displayed are read from memory 1 by sequentially iterating through its addresses at a frequency

TV sweep with reading address counter 10. Counting pulses come either to the summing input or to the swithing input of the last counter from the outputs of the switch 8, to

the inputs of which they come from the first input of the former 22 of the sweep function horizontally. The switch 8 is controlled by its address input;

determined by the state of register 7, the bit of information to which comes from the n-th bit of the computer data bus,

When a frequency arrives at the summing input of the counter 10, the reading address information on the screen of the indicator 5 is placed in the order of the sequence of the body 1 to read them from left to right and from top to bottom, starting from the upper left corner of the indicator screen. When a clock frequency arrives at the subtracting input of the counter 10 of the reading address, the information displayed on the screen of the indicator 5 is placed relative to its location when the clock frequency is received at the summing input of the last counter (Fig. 3g, n). Combining the most different combinations of symbol display options: turning from left to right or from top to bottom and direct or reverse reading of information from memory 1, you can get on the display of the indicator 5 the most geometrically different displays of graphic information of 1-D1N models. the minimum volume of the memory block 1 and the ROM 18. The writing of the character codes in the memory block 1 is carried out at intervals of retraction along the frame of the beam of the television indicator 5 (duration of the IGG), at this time the OIG from the second TV output with a high level generator of the third input of the switch 9 connects the address input of memory block 1 to the output of the computer address address, and simultaneously the third one of memory block 1 (write-read input) initiates the latter for recording information At the zero level on the specified inputs (during the absence of an IGL pulse, i.e. during the forward stroke of the sweep of the beam of the television indicator-torus 5) the memory cells of the memory 1 are read. At this time, the switch 9 connects the address output of the reading address counter 10 to the address input of the indicated memory block, and the reading mode is initiated at the third input of the memory 1. The pulses of the illumination of the CRT beam of the television indicator 5 are fed to the first input of the video signal shaping unit 4, where they are summed with the signal of the standard television synchro mix received from the third output of the clock generator 24 to the second

the input of block 4 of the formation of video messages, and the full television video signal is fed to the indicator 5 for further display on its screen.

Claims (1)

The clock generator 20 produces pulses of the horizontal sampling rate of an image, the period of which is equal in duration to the smallest element of the symbol discretization horizontally. At the same time, the act generator 20 generates a reference frequency necessary for the operation of the clock generator 24. It enters the input of the specified clock of the clock generator after dividing by frequency divider 23 which divides the horizontal sampling frequency to a value (for example, 2 MHz), which is necessary for the work of the standard clock generator 24. Frequency horizontal das. - the elementization of elements of the element is fed to the first, which is the counting, the input of the counter 21 horn: tO 1t; 1b; oh discretization. String-outpulse and after posting the second counter of the last counter from the first output of the synchroheprator 24, the counter 21 of the horizontal 1 sampling rate is set to the zero state. Shaper-22 razzertyva: this horizontal function forms from the output signal of the counter 2 horizontal sampling and; - - PU-1bC) -1-yy sequences of the frequency: polling polling of pp cells; - g: b; tlka 1 memory in read mode and tact ; oh shift frequency, the record of the shift information in the registers 3; 15 sdv: 1 hectare right and left. The first one from the first output of the imaging unit 2 and; -a screwing-up function by horizontal post via the switch 5 either to or to the readout inputs of the reading address counter 10, and BtopaH from the second 1-o-dürmiromator 22 the horizontal sweep function enters the second (clock) inputs shift information shift registers 3 m 4 Right and left. 1 The proposed device allows you to get on-screen television indicator supplement; 1 to; The images are symmetrical to the main ones, which broadens the scope of its application, especially when displaying diagrams, mnemonic diagrams, genotypes::: m, bar graphs and other images that have a symmetrical structure. In addition, the device also makes it possible to reduce the volume of the character generator ROMs, which makes it possible to simplify the device as a whole. The invention The device for displaying information on a television indicator containing a memory block, the first input of each is the first input of the device, the first output of the memory block is connected to the first input of the symbol generator, the first output of which is connected to the first input of the first shift register, the first the output of the synchronization unit is connected to the first output of the first switch, the second output of the synchronization unit is connected to the first input of the generation unit, video signals, the output of which is connected to the television indicator ., t, lchayuscheesya the fact that, with a view simplifying the device and expanding the area of the device; 1-5 changing the device, due to the possibility of displaying images symmetrical to the main one, it contains the first, second and third registers, the second, third and fourth switches, the reading address counter, the row counter and the second shift register, the output of which connected to the first input of the second switch, the second input of which is combined with the output of the first shift register, the input of the second switch is connected to the second .. The second input of the device, the third input of the fourth switch is connected to the output of the reading address counter, the output of the fourth switch is connected to the third input of the memory unit, the input of the third register is the third input of the device, the output of the third register is connected to the second input of the nepfioro switch the first and second outputs of which are connected to the first and second inputs of the reading address counter, respectively. "7 eye input of the video signal conditioning unit, the first input of the second shift register is connected to the first output of the character generator, the second output of which is connected to the first output of the third switch, the input of which is connected to the second input of the character generator, the third input of which is connected to the input of the row counter and the third the input of the synchronization unit, the fourth output of which is connected to the second inputs of the first and second shift registers; the output of the row counter is connected to the second input of the third switch, the third input of which is connected with the output of the first register, the input of which is connected to the second output of the memory unit, the third input of which is connected to the input of the second register; the output of which is connected to the third input of the second switch; the fifth output of the synchronization unit is connected to the second input of the memory unit and to the first input of the fourth switch whose second input is ow ff EZ and 669 .ag.Z