SU1279080A2 - Transmitting device for statistic multiplex communications system - Google Patents

Abstract

The invention relates to a communication technique that can be used to integrate multi-channel communication systems with pulse code modulation. The goal is the quality of voice transmission. The transmitting device contains a block matching 1 clock speed, input shift register (PC) 2, PC 3 count, compare block 4, threshold block 5, write control unit (CU) 6, switch 7, intermediate storage register 8, CU 9 read, block 10 sync signals, memory unit 11, counter 12, descrambler, torus 13, shift control unit 14, shift registers 15 and 17 of the combined cycle and the converted cycle, ring PC 16 and delay unit 18. The goal is achieved by inserting two counters 19 and 20 units, two triggers 21 and 22, a decoder 23 states of triggers, two elements: comrades NOT 24 and 25, two elements AND 26 and 27, aleme} 1ta OR 28, descramble for? (L

Description

with about

00

1H

29 zeros, a reversible counter 30 and a delay element 31, with which the device in adaptive mode monitors changes in the information load at the system input,

due to both an increase (decrease) in the number of supported voice connections and the transition of subscribers to the active or to the passive state. 1 il.

Claims (4)

The invention relates to a communication technique that can be used to integrate multi-channel communication systems. pulse-coded modulation and is an improvement of the known device auth.St. No. 1181158. The purpose of the invention is improving the quality of voice transmission. The drawing shows the structural scheme of the proposed device. The transmitting device contains a clock rate matching unit 1, an input shift register 2, a reference shift register 3, a comparison block 4, a threshold block 5, a recording control block 6, a switch 7, re, intermediate storage histor 8, a read control block 9, the sync signal generating unit 10, the unit 11pam, the counter 12.:. a decoder 13, a shift control block 14, a combined cycle shift register 15, a shifting ring register 16, a converted cycle shift register 17 and a delay block 18, 19 and 20 counters, triggers 21 and 22, a decoder 23. state of triggers, NOT elements 24 and 25, elements AND 26 and 27, element OR 28, a decoder 29 zeros, a reversible counter 30 and a delay element 31. The transmitting device operates as follows. Pulse-code modulation (PCM) signals are transmitted to the wiring blocks of the unit 1, which performs the channel-by-channel unification of digital streams. At the output of block 1, a signal is generated that has a modulation rate corresponding to the sum of the speeds of the incoming digital streams, with in the course of block 1 a digital stream arrives at the input of the shift register 15, having a capacity equal to the length of the combined transmission cycle, information in pa The parallel code is rewritten to the ring register 16 by the sync pulse from block 10, which arrive at a frequency equal to the sampling frequency. The same clock signal is fed to the input of block 18 and to the input of counter 12, which has a conversion factor of 2 N. The amount of the sum in parallel code from counter 12 is fed to the input of the decoder 13. Ssch-Nal from the corresponding excited output of the decoder 13 (number of the excited output corresponds to the number of samples, but which the combined cycle needs to be shifted to the right) goes to block 14, to the other input of which pulses are received with a frequency specifying the shear rate in the ring register 16, the frequency of these pulses is selected avnoy product of frequency-doubled disk-retizatsii dl1dau on the combined cycle. This frequency value provides information shift in the ring register 16 by (2N-1) bits during a time equal to (T / 2), where T is the period of the combined cycle. After the shift, the information from the ring register 16 is rewritten into the shift register 17. The moment of rewriting is determined by the presence of syn. the output signal of block 18, in which the delay time is equal to T (3/4) T. This ensures the rewriting of information from the ring register 16 to the shift register 17 before writing the next combined cycle to the ring register 16. From the shift register 17, the information is sequentially read under the influence of clock signals with a frequency f2 f, "2 NK, coming from block 10, where f, - sampling frequency. The bits of the input register 2 are fed to the input of the register 3 with a capacity of K bits. The signals from the outputs of register 3 and the outputs of the bits of the input register 2, having numbers from (K-1) to 2K, are fed to block 4, at the output of which a signal is generated in a parallel code equal to the absolute value of the difference between the previous and current samples of the i-ro channel. From the output of block 4, the signal arrives at the input of threshold block 5, which, at the instants of time determined by block 10, generates a signal 1 at its output when the threshold value f or 0 is exceeded - in opposite case. The signals from the output of the threshold block 5 are fed to the input of block 6 and the corresponding input of the switch 7, to the other inputs of which are fed in parallel code signals from the bits of the input register 2 with numbers from (K + 1) to 2K. Block 6 at time points determined by block 10 generates control signals by which switch 7 records the current value of channel samples (the difference of which with previous values has exceeded the value determined by threshold block 5) and signals O and 1, formed at the output of the threshold block 5 into the information and service fields of register 8 allotted for these purposes. Register 8 has a capacitance (KN-M) of bits, where the number of bits allocated for the device's cycle-phasing clock signal. To transmit update information, (KN-2N-Mj,) is allocated to the bits in each output cycle. In addition to the sync signal, in each output cycle, a service word with a capacity of 2 bits is transmitted, which indicates in which channel intervals of the combined digital stream the absolute value of the difference in counting values of the current and previous cycles of the corresponding channel intervals exceeded the threshold value. : At the time of the end of the comparison, the sample values of all the time slots of the previous and current combined transmission cycles, information from register 8 is rewritten to block 11. It carried out sequential reading of information from the cells of block 11 ,. block 9 forms a transmission cycle. The capacity of block 11 is K-N bits. 804 The device operation in the adaptive mode is designed to track changes in the information load at the system input, due to both an increase (decrease) in the number of voice connections that are / are maintained and a transition of subscribers to active or passive state. Information to judge the current value of the incoming load is the number of units in the control word that were formed at the output of the threshold block 5 for the duration of the combined cycle. If the number of units in the control word exceeds the number of time slots that are used in the device to transmit the update information, this suggests that the current threshold value is not enough and needs to be increased. Otherwise, the threshold value must be reduced. In order to avoid frequent adjustments, the device must keep the threshold value unchanged if the number of units in the control word is within the established limits. The operation of the device in adaptive mode provides four possible cases: 1. An increase in the threshold value by one in the threshold unit 5 is performed if the number of units in the service word is more than M, where M5 is some upper limit. 2. The reduction of the threshold value by one in the threshold block 5 is performed if the number of units in the service word m is M, where M is some lower limit. 3. The preservation of the threshold value in the threshold block 5 at the same level is performed if the number of units in the service word satisfies the condition. 4. The lower bound of the threshold value E is zero, i.e. The orog value in threshold block 5 cannot be a negative number. The choice of the values of M and M is carried out from the condition where the M e is the canal intervals used in the device for the transmission of the feedback information. Thus, the window defined by the values of M and affects the frequency of restructuring of the thresholds in the threshold block 5. 5127 the quality of speech exchange and the number of threshold reorganizations decreases. 1st case. In threshold block 5, a certain threshold value t.0 is set. Signals or O from the output of the threshold unit 5 are received in parallel to the inputs of counters 19 and 20 with the conversion factors M and M (respectively. These counters 19 and 20 count the number of units recorded; in the service word. They are the same as the triggers 21 and 22 are set to the zero state at the end of each combined cycle by a signal arriving at the corresponding inputs of the installation in O from the corresponding additional output of the block 10. When the counters 19 and 20 M, and Mj are received at the input, respectively, transfer pulses are formed a, through which the flip-flops 21 and 22 are set to one.Signals from the direct outputs of these flip-flops 21 and 22 form a combination 11, which is fed to the input of the decoder 23. This combination corresponds to 1 at the third output-decoder 23s which is fed in parallel to the control input of the reversible counter 30, transferring it to the summing mode, as well as to one of the inputs of the element 27, allowing the passage of a sync pulse coming from block 10. Thus, the state of the reversing counter 30 at the end of the intermittent cycle will increase 1. At the same sync pulses from the secondary output block 10 at the end of each cycle through a combined transmission element 31 zaderzh1si schetchshsh 19 and 20, flip-flops 21 and 22 are set to the zero state. The signal of the new threshold value at the next interrupted clock in the form of a K-bit code comes from the outputs of the reversible counter 30 to the corresponding inputs of the threshold unit 5, changing the threshold value in it to the duration. next combined transmission cycle. 2nd case. In threshold block 5, a certain threshold value is set. Since the number of units in the case under consideration is in the CJ transient word, cM, then at the outputs of both counters 19 and 20 a transfer pulse is not formed and the flip-flops 21 and 22 remain 06 in the zero state in which they were installed at the end of the previous combined cycle. At the inputs of the decoder 23, the signals from the direct outputs of the flip-flops 21 and 22 form a combination 00, which excites the signal 1 only at its first output connected to the second input of the HE element 25, the first and second outputs of which also have the resolving potential from the outputs of the HE 24 and 25 respectively. The latter ensures the passage of a sync pulse, the input element NE 25, 3 of block 10. At the same time, the potential on the control reversing account C 30, coming from the output of the decoder 23, keeps it in the subtraction mode. Thus, when a sync pulse arrives, the contents of counter 30 are reduced by 1. 3rd case. Since the number of units in the service word is M, then a transfer pulse is generated at the output of the first counter 19, which is set. The zero state of trigger 21, in which it was set at the end of the previous combined cycle, goes to zero. At the outputs of the decoder 23, the signals from the direct outputs of the flip-flops 21 and 22 form a combination 01, which excites the signal 1 only at its second output. This signal 1 is inverted by the NOT element 25, which prohibits the passage of a sync pulse from block 10 through the element 26. And in addition, the signal on the third output of the decoder 23 also prohibits the passage, the sync pulse through the element I 27. . ensures the preservation of its state and the preservation at the same level of the great threshold, the case. In threshold block 5, threshold is set to 0. Since the number of units in the service word M, the triggers 21 and 22 remain in the zero state, the output of the decoder 23 signal 1 is present only at its first output. The signal O from the third output of the Deshfratora 23 prohibits sihihro through the element I 27 to the input of the reversing counter 30 through the epement OR 28. The signal 1 from the output of the decoder 29, which turns the clock signal, prohibits the passage of a sync signal. This ensures that the value of the reversible counter 30 is set to zero, i.e. the value of EO for the next combined cycle remains the same. Claims of Invention A transmitter for a statistical compression communication system according to the author. No. 1181158, which means that, in order to improve the quality of voice transmission, the first unit counter, the first trigger, the state decoder of the trigger, the first element NOT, the first element AND, the element OR, reversible counter, decoder zeros, the second element is NOT, the output of which is connected to the second input of the first element And serially connected second counter of units and the second trigger, the output of which is connected to the second input of the state decoder of the trigger state, the delay element whose output is connected The second input of the second input of which is connected to the second code of the state trigger decoder, and the output to the second input of the OR element, the third output of the state decoder of the trigger trigger is connected to the third input of the first element AND, the output of the threshold unit connected to the combined inputs of the counters of units, the additional output of the block, the formation of the sync signals is connected to the input of the delay element with the fourth input of the first element And the second input of the second element And, with the output reversible The second counter is connected to the control input of the threshold unit.