SU1272510A1 - Redundant pulse generator - Google Patents

Abstract

This invention relates to electronic digital systems with redundancy. It can be used as a clock distributor in combination with a master oscillator under conditions of random failures. The purpose of the invention is to increase reliability and enhance functionality. The device contains a driver 1, a driver 2 backup, a driver 3 control, drivers 4 and 5 pulses, output stages 6 and 7, blocks 9 and 10 of the comparison. To achieve this goal, an element NOT 8, an element AND-NOT 11, counters 1416 are introduced into the device. The device allows to distinguish faults from failures, 1 Il. cl

Description

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The invention relates to electronic digital systems with redundancy and can be used as a clock distributor in conjunction with a master oscillator in order to accidentally fail.

The aim of the invention is to increase reliability and enhance functionality.

Improving the reliability is achieved due to the fact that when the control driver fails and when the working driver works properly, the load does not switch off and does not change the mode of its operation, and also due to the fact that all three drivers are put into synchronous operation

The functionality extension is achieved due to the fact that the device distinguishes failures from failures.

The drawing shows a functional diagram of a redundant pulse generator.

. The device contains a working driver 1, a backup driver 2, a control driver 3, drivers 4 and 5 pulses, output stages 6 and 7, element 8, comparison units 9 and 10, element AND-NOT 11, elements 12 and 13 of memory, counters 14-16, input bus 17, output tires 18-20.

Input bus 17 is connected to clock inputs of drivers 3-5, information outputs of drivers 4 and 5 are connected respectively to inputs of output stages 6 and 7, the outputs of which are connected to output bus 18 and to the first input of comparison unit 9, information output of driver 5 is connected to first , the input unit 10 of the comparison, the output of the imaging unit 3 is connected to the second inputs of the units 9 and 10 of the comparison, the output of the last of which is connected to the first input of the element AND-NOT 11, to the input of the stop of the imaging unit 3 and to the information input of the memory element 12 and; the output of the element HE 8 is connected to the input of the resolution of the output stage 7 of the reserved generator 2 and with the second input of the element AND-HE 11; the output of the comparator unit 10 is connected to the inverse input of the element AND-HE 11, the output of which is connected to the stop input of the imaging unit 5 and to the information input of the memory element 13; exits

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elements 12 and 13 of the memory are connected respectively to the counting inputs of the counters 14 and 15, the installation inputs of which are connected to the output of the counter 16; the installation input of which is connected to the output of the counter 14; with output bus 19, with the input of the HE element 8 and with the input of the output of the output stage 6 of the working driver 1, the control output of the driver of which 4 pulses are connected to the reset input of the memory element 13 and with the counting input of the counter 16; the control output of the imaging unit 5 is connected to the reset input of the memory element 12, the output of the counter 12 is connected to the output bus 20.

The output of the first counter 14 is the alarm output of the working driver 1 or the control driver 3, and the output of the second counter 15 is the alarm output of the redundant driver.

The working driver 1 is designed to form certain pulse sequences and consists of a driver 4, which can be performed on a counter or a frequency divider, and an output stage 6, used to amplify pulse sequences and for their switching depending on the enable signal from the output of the counter 14 .

The output stage 6 consists of the cascades of amplification of the pulse sequences coming from the imaging unit 5 and the transistor connecting and disconnecting the power from these cascades via a signal received at the resolution input from the counter 14. When the input of the resolution is received, the logical O transistor opens and energizes the amplification stages. and thus the output driver 1 is connected to the output (including the load), and when the logical 1 is input to the input, the transistor closes, the power from the stages is disconnected power and working driver 1 is disconnected from the output.

The redundant driver 2 is made similarly to the working driver 1 and consists of the driver 5 and the output stage 7. 312 Control driver 3 is made similarly to driver 4 and 5, Comparison blocks 9 and 10 are designed to determine the synchronization (phase identity and pulse duration) of pulse sequences, arriving respectively from the working and control drivers 1 and 3 to the comparison block 9 and from the redundant and control drivers 2 and 3 to the second comparison block 10. During synchronous operation of all the formers 3-5 at the output of blocks 9 and 10 comparison is logical 1, in the absence of synchronous operation of the formers 1 and 3 at the output of block 9 comparison is logical O, in the absence of synchronous operation of the formers 2 and 3 at the output of block 10 comparison logical O.

The memory element 12 is designed to memorize the absence of synchronous operation of the formers 1 and 3 during one cycle of operation of the reserved generator 2, the memory element 13 is intended to memorize the absence of the synchronous operation of the formers 2 and 3 during one cycle of the working generator 1. As elements 12 and 13 memories can be used, for example, the installation triggers on the two NANDA elements. At the end of each cycle of operation, the redundant driver 2 delivers from the control output a pulse (logic O) of reset and the input of the memory element 1 2, analogously at the end of each cycle of operation, the working driver 1 supplies from the control output an impulse (logical O) to the reset input of the memory element 13. By the indicated reset pulses, the memory elements 12 and 13 are set to the initial state (logical 1 at the output) corresponding to the synchronous operation of the compared drivers. The information inputs of the memory elements 12 and 13 receive information respectively from blocks 9 and 10 of the comparison. For all the time of synchronous operation of the formers 1 and 3, the information input of the memory element 12 receives a logical 1 and the output of this element is a constant - logical 1, i.e. there are no pulses at the counting input of the counter 14, and when these drivers are unsynchronized, the information input is the counting pulse of the first counter 14. Memory element 13 works in a similar way.

The counter 14 is designed to count the number of operation cycles of the redundant imager 2, during which time the asynchronous operation of the formers 1 and 3 outputting a malfunction signal of the worker 1 or the monitoring 3 of the formers was observed, through which the imaging device 1 is disconnected from the bus 18 and the redundant imager 2 is connected.

The counter 15 is designed to count the number of work cycles of the working driver 1, during which the asynchronous operation of the reserved 2 and control 3 drivers was observed, and a signal about the failure of the redundant driver 3 was observed.

The counter 16 is designed to generate the installation pulses to the initial state of the counters 14 and 15, which is necessary to prevent the accumulation of information about the number of desynchronization of the corresponding drivers caused by random failures for a long time.

The counter 16 generates the pulses for installing the counters 14 and 15 into the initial state by dividing the frequency of the pulses arriving at its counting input from the working driver 1 at the end of each cycle of its operation. The installation signal of the first and second counters is also generated in the initial state when a signal (logical O) arrives at the Reset input from an external device (not shown). When synchronizing operation of drivers 1 and 3, counter pulses 14 are not present at the counting input, and the installation pulses from the counter 16 and set the counter 14 to the initial state (at the output - logically O). Asynchronous operation of the module is about 10%, the element drops logical is set to the opposite state (output - logical O), which is preserved / then the arrival of the reset pulse from the reserved form. worldr 2, Thus, during the asynchronous operation of the formers 1 and 3, during one cycle of operation of the imaging unit 5, at the output of the memory element 12, one emu lei 1 and 3 counter 1- counts the number of pulses from the memory 12 a certain number of pulses (during asynchronous operation of drivers for more than a certain time) at the output of counter 14, a signal is generated (logical 1) that a worker 1 or control 3 drivers fails, counter 14 is self-blocked (disabled the lowest pulse counting), resetting the counter 16 to the initial state (disables the pulse shaping of the setup), disconnecting the working driver 1 from the bus 18, and connecting the redundant driver to the bus 18 Similarly, the counter 15 operates and generates a signal about the failure of the backup driver 2 during asynchronous operation reserved 2 and control 3 shapers over a certain time. The HE element 8 is intended for simultaneous connection to the bus 18 of only one of the formers 1 or 2. The AND-NE 11 element is intended for prohibiting the monitoring and stopping of the redundant driver 2 in the presence of asynchronous operation of the driver 1 and 3 (logical O is at the output of -Ka 9 comparison) or when fixing a malfunction of the formers 1 and 3 (logical O - the output element is NOT 8). The device works as follows. When the power is supplied to the Reset input (not shown), a short-time signal is given by which the counter 16 generates a setup signal to the initial state, by which the counters 14 and 15 are reset, the working driver 1 is connected to the bus 18 and the redundant shaper 2. When a pulse sequence device arrives at the bus 17, all shapers 1-3 start working. At the initial moment, all formers 1-3 work asi are chronically one relative to the other. In this case, at the output of block 9 of comparison, a signal is formed (logical O), indicating that the shaper 1 and 106 are working in a bad way, which stops the control driver 3 and according to which memory element 12 generates a signal (logical O) at output; the counter pulse for counter 14, and the first counter detects the presence of the first failure. The signal from the output of the comparison unit 9 is fed to the first input of the NAND 11 element and the stop signal of the redundant driver 2 is prohibited, although a signal (logical O) is generated at the output of the comparison block 10, indicating asynchronous operation of the drivers 2 and 3. Control driver 3 remains stopped until the working driver 1 in the process of operation takes the position equal to the position of the stopped control generator 3, after which a signal (logical 1) is formed at the output of the comparison block 9, the identity of signals from drivers 1 and 3, which later enables the control driver 3 and, arriving at the first input of the element I-HE 11, removes the prohibition of stopping the redundant driver 2. At the same time, drivers 1 and 3 start to work synchronously, and the control drivers continue to remain out of sync with each other. At the output of the comparison unit 10, a signal is formed (logical O), which is fed to the inverse input of the AND-NO element 11, a signal is generated at the output of this element (logical O), which stops the redundant driver 2 and by which the memory element 13 generates The output signal (logical O), which is the counting pulse for counter 13, and the second counter captures the first failure. The redundant driver 2 remains stopped until the control driver 3 reaches the position equal to the position of the stopped backup formation 2, after which a signal (logical 1) is generated at the output of block 10, indicating the identity of the signals of drivers 2 and 3, which further allows the operation of the reserved imager 2. In this case, all three generators 1-3 begin to work synchronously. Thus, when the three shapers 1–3 are unsynchronized, their synchronization occurs in stages: at the beginning, the shapers 1 and 3 are synchronized, then the shapers 2 and 3. Similarly, the desynchronization of only the working driver 1 or B at the beginning of the cases, the control driver 3 is stopped and entered into synchronization with the working driver 1, after which the redundant driver 2 is stopped and entered into synchronization with the control form generator by telem 3. When only the redundant driver 2 is unsynchronized, its input into synchronous operation is carried out in one stage, i.e. it stops sticking and being synchronized with the control driver 3. When any driver fails to synchronize, the working driver 1 does not stop and thus the device is continuously operating on the load. Information on the number of failures accumulated in the counters 14 and 15 is erased by the installation pulse from the counter 16 for the synchronization time. When the working driver 1 fails, the output of the comparison block 9 generates an unequal signal of the drivers 1 and 3, which stops the control driver 3 and stops it - reserved form, worldizer 2. In this case, the memory element 12 forms each cycle of the operation of the reserved pulse former 2 generator, which is the counter 14 pulse. After the arrival a predetermined number of pulses, the counter 14 generates a signal about the malfunction of the formers 1 and 2, which prohibits further counting of the pulses, prohibits the shutdown of the reserved former 2, disconnects the load from the working driver 1 and connects the load to the load the reserved imager 2, returns the counter 16. malfunction of the formers 1 and 3 is provided via bus 19 to the external device ..

Similarly, the device operates when the malfunction of the control driver 3.

Claims (2)

Nor, characterized in that, in order to increase reliability and increase functionality by providing an opportunity to distinguish failure from failure, three counters are entered into it, the NOT element, the AND-NOT element, the first information output of the redundant imager is connected to the first information output of the operative imager , the output of the control former is connected to the second inputs of the first and second comparison blocks, the output of the first comparison block is connected to the input stop of the control former and the first input element This IS-NOT, the second input of which is connected to the output of the NOT element and to the resolution input. If the redundant generator 2 fails, the output of the comparison unit 10 generates a signal of unequal signals of the drivers 2 and 3, according to which the element AND-NOT 11 forms a signal of the redundant generator 2. In this case, the memory element 13 generates a pulse for each cycle of operation of the working generator 1, which is the counter counting pulse 15. After the arrival of a certain number of pulses, the counter 15 generates a signal about the malfunction of the reserved generator 2, which prohibits further pulse counting. The failure signal of the reserved driver 2 is signaled via bus 20 to an external device. Bus 8 is left connected to bus 8. Claims redundant pulse generator containing two memory elements, an input bus that is connected to the clock input of the control driver, and also the clock inputs of the working and redundant drivers having the first and second information outputs and the control output, the first information output of the working driver with the first output bus, with the first input of the first comparison unit, the output of which is connected to the information input of the first memory element, the second information output one of the reserved imager is connected to the first input of the second unit; compare 9, 127251010 the redundant driver, output counter and the output of the third reference unit are connected to a pickup, the installation input of which is connected to the input of the NAND element, you with the output of the first counter, p. the stroke of which is connected to the informational-second output bus, with the input by the eilenny input of the second memory element of the HE mode and the working permission input and with the stopper input of the backup generator, the control output of which is the driver, the control output is connected to the counting input of the track unit which is connected to the reset input of its counter and to the reset input of the second the first memory element, the output of a memory element, the output of which is connected to the counting input is per-Junen with the counting input of the second counter, the second counter, the input of which is the output of which is connected to the third The go is connected to the installation input by a second output bus.