SU1264163A1 - Modulo 3 adder - Google Patents

Abstract

The invention is intended for control systems used in automation and computing. The aim of the invention is to extend the functionality by generating modulo three residues for N-bit input words coming in consecutively four bits. In the modulo-three adder, a modulo-three deduction is generated for the input bit words coming in four bits. The device contains two triggers, two logical elements EXCLUSIVE OR, element OR-NOT and a decoder. The use of the logical element And and the decoder made it possible to reduce the time of formation of residues for N-bit input words and to extend the functionality by forming calculations of three moduli for four times (regular input combinations. 2 ill.

Description

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with

The invention relates to automation and computing and can be used in control systems.

The purpose of the invention is to expand the functional possibilities by organizing residues for four-bit input combinations.

Figure 1 presents the block diagram of the adder modulo three, figure 2 shows the transition graph of the adder modulo three.

A modulo-three adder (FIG. 1) contains the first and second triggers 1 and 2, the first and second elements EXCLUSIVE OR 3 and 4, the WN-NOT 5 element and the decoder 6, the first 7, the second 8, the third 9 and the fourth 10 information inputs , first 11 and second 12 outputs of the result.

The adder works as follows.

On the graph (Fig. 2), the vertex numbers 0,1,2 correspond to the values of the sum modulo three. Arcs show the directions of transitions when arriving at the inputs of a modulo-three all input combinations specified

| 1mi fj x XjXj 3 Vx j jX2XjV x XjXjX vx XjXjX vXj, JCjXj x., XjX2Xj ;.

f j X X Xj X. (V x Cd Xj X V X Xj Xj X V / X Xj Xj X V X Xj Xj X V XjSj X V X4XxX | XY, X

where the eldest is with weight 8, Xj is with weight 4, X2 is with weight 2, x is with weight-. Som 1 rank of these combinations. The modulo three sum is encoded by the states and the T2, T1 triggers as follows: O - 00, 1 - 01, 2 - 10, the trigger states are denoted by aj a (aj is the highest with a weight of 2, and the younger with a weight of 1 amounts). In the initial state, the triggers T1 and T2 are in the zero state (the circuit for setting the triggers to the initial state in FIG. 1 is not according to KasaHbJ). In each cycle of operation, the triggers are first in a certain current state CL, oh. Corresponding to the modulo sum of all the previously received input combinations x XjXjX, Then to the first 7, three times 8, third 9 and fourth 10 inputs arrive, respectively, Xj, Xj, X., the bits of the input combination, under the influence of which the triggers go into the next state, which determines the sum modulo three of all the input combinations including the work received in this cycle.

From the transition graph, it can be seen that when the x комбина XjXjX combinations of specified functions fj arrive (with bit values of 0000 OOP, 0110, 10001 1111), modulo 3 does not change and the triggers do not change their states. In this case, the synchronization signal on the Triggers of both triggers is zero. In the remaining cases, the synchronization signal at the C inputs of the triggers is 1, and the triggers can change their state when the input combinations specified by the functions fj and f 3 arrive.

Transitions of triggers of the adder modulo three of all possible current states of a., Ai (00, 11, 11) to the next skh a state for different values of the input combinations

x XjX2Xi are shown in the table. It also shows the values of the synchronization signals (c) at the C inputs and the signals at the I and K inputs of the first II, K1 and second 12, K2 triggers that provide these transitions. The values of signals II, 12 are given for those cases where the current state of the trigger, ger, is 01, 10. The synchronization signals (C) and the signals at the K-inputs coincide and do not depend on the current state of the triggers.

000000 O O 01 O 1

000101 1 О 10 1 1

Oh oh

one

About 1

About 1 About About 1

The values of signals II and 12 are formed with the help of the EXCLUSIVE OR elements and the decoder, and the values of the signals C, K1 and K2 - with the help of the decoder and the element SH-N. For stable operation of the modulo-three adder, it is necessary that the duration of the signals of the input combinations should not exceed the sum of the times of one trigger and one element EXCLUSIVE OR.

The decoder can be implemented according to a known scheme.

Formula and 3 obrat shadows

A modulo-three adder containing the first and second elements EXCLUSIVE OR, and the first and second 1K-triggers, with T-entering the first and second Continuation of the table

triggers are connected respectively to the outputs of the first and second elements EXCLUSIVE OR, the C and K inputs of the first and second 1K triggers are interconnected, the forward outputs of the first and second triggers are outputs of the result of the adder, characterized in that expansion, functionality due to the formation of modulo residues for four four-slot 1d input combinations, a CIN-HE element and a decoder are introduced into cyi iaTop, the first output of the decoder is connected to the first input of the IPI-NE element, the second output of the cipher ora connected to the first input of the second element ISKLKNASCHEE OR, third output of the decoder is connected to a first input of the first exclusive-OR gate, fourth output of the decoder is connected to a second input of OR-NO element, a fifth output decoder connected to the second input of the second element ISKLYUCHANSHSCHE OR sixth output of the decoder connected to the second input of the first element EXCLUSIVE OR, the seventh output of the decoder is connected to the third input of the element OR NOT, the eighth output of the decoder is connected to the third input of the second element EXCLUSIVE AND WHERE, the ninth output of the decoder is connected to the third input of the first element TRAINING OR, the tenth output of the encoder is connected to the fourth input of the IPI-NE element, the eleventh output of the decoder is connected to the fourth input of the second element EXCLUSIVE OR, the twelfth output of the decoder is connected to the fourth input of the second element and the twelfth output of the decoder to the fourth input of the second input is connected to the fourth input of the second element EXCLUSIVE OR; OR, the thirteenth output of the decoder is connected to the fifth input of the element OR NOT, the fourteenth output of the decoder is connected to the fifth input of the second element EXCLUSIVE W) the fifteenth output of the decoder oedinen to a fifth input of the first OR element ISKLOCHANSCHEE sixteen decoder output is connected to a sixth input of the NOR straight 1K output of the second flip-flop is connected to a sixth input of the first exclusive OR output of the first straight element. The 1K flip-flop is connected to the sixth input of the second element EXCLUSIVE OR the output of the OR element is NOT connected to the C K inputs of the first and second IK triggers, the first, second, third, and quarter inputs of the decoder are the inputs of the adder.

Claims (1)

Claim The modulo three adder contains 55 the first and second EXCLUSIVE OR elements and the first and second 1K triggers, with the 1 inputs of the first and second EXCLUSIVE OR elements, the C and K inputs of the first and second 1K triggers connected to each other, the direct outputs of the first and second triggers are the outputs of the adder result, characterized in that, in order to expand the functionality due to the formation of residues modulo three for four-digit input combinations, an OR-NOT element and a decoder are introduced into the adder, the first output being a decoder torus is coupled to a first input of OR-HE, the second output of the decoder is connected to a first input of the second exclusive OR element, the third output of the decoder is connected to a first input of a first IC element s KEY OR, the fourth output of the decoder is connected to the second input of the element OR-HE, the fifth output of the decoder is connected to the second input of the second element EXCLUSIVE OR, the sixth output of the decoder is connected to the second input of the first element EXCLUSIVE OR, the seventh output of the decoder is connected to the third OR , the eighth output of the decoder is connected to the third input of the second EXCLUSIVE OR element, the ninth output of the decoder is connected to the third input of the first element EXCLUSIVE OR, the tenth output of the decoder is connected from the fourth m the input of the OR-HE element, the eleventh decoder output is connected to the fourth input of the second EXCLUSIVE OR element, the twelfth decoder output is connected to the fourth input of the first EXCLUSIVE OR element, the thirteenth decoder output is connected to the fifth input of the OR-HE element, the fourteenth output of the 5th decoder is connected the input of the second element EXCLUSIVE OR, the fifteenth output of the decoder is connected to the fifth input of the first element EXCLUSIVE OR, the sixteenth output of the decoder is connected to the sixth input of the OR-HE element, direct the output of the second IK trigger is connected to the sixth input of the first EXCLUSIVE OR element, the direct output of the first 15 IK trigger is connected to the sixth input of the second EXCLUSIVE OR element, the output of the OR-HE element is connected to the C K inputs of the first and second triggers, the first, second, the third, ²⁰ fourth inputs of the decoder are the inputs of the adder. Phil