US4907171A  Image size converter  Google Patents
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 US4907171A US4907171A US07031038 US3103887A US4907171A US 4907171 A US4907171 A US 4907171A US 07031038 US07031038 US 07031038 US 3103887 A US3103887 A US 3103887A US 4907171 A US4907171 A US 4907171A
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 G06—COMPUTING; CALCULATING; COUNTING
 G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
 G06T3/00—Geometric image transformation in the plane of the image, e.g. from bitmapped to bitmapped creating a different image
 G06T3/40—Scaling the whole image or part thereof
Abstract
Description
The present invention relates to an image size converter for reducing or enlarging image data.
A conventional image size converter such as that shown in FIG. 1 includes a Digital Differential Analyzer (DDA). The DDA is a known circuit for generating coordinate values from an initial scale value and an increment scale value. The DDA includes adder 14, scale register 15 in which a reduction or enlargement ratio of an image size is set, and accumulator 16 in which "0" is set as an initial value and then a decimal part is set.
The image size converter also includes logic circuitry connecting the DDA to a source register 11 and a conversion pattern register 13. AND gate 1 gates a carry signal from adder 14 during reduction of the image in the reduction mode, and AND gate 2 gates a carry signal from adder 14 during enlargement of the image in the enlargement mode. The logic circuitry also includes OR gate 4 for continuously supplying a shift signal to source shift register 11 (to be described later) in the reduction mode, OR gate 3 for continuously supplying a shift signal to destination register 13 in the enlargement mode, and AND gates 6 and 5 for gating the shift signals from OR gates 4 and 3, respectively. Source shift register 11 stores image data, data generator 12 (e.g., OR gates) receives an image dot pattern from register 11 and generates an image data pattern representing an enlarged or reduced image dot pattern, and destination register 13 stores image data output from data generator 12.
In order to reduce image data in the circuit of FIG. 1, image data output from source shift register 11 in units of dots is extracted (or logically ORed) by data generator 12 at a predetermined rate. Image enlargement is performed by copying the same image data to destination shift register 11 until a significant carry signal is supplied thereto. Image data enlargement and reduction in the conventional image size converter will be described below. It should be noted that the circuit in FIG. 1 is operated according to the normal logic, i.e., active high.
To understand the operation of the system of FIG. 1 in the reduction mode, assume that the image size is to be reduced to 1/3. In this case, value "1/3" is set in scale register 15, and "0" is set as the initial value in accumulator 16. Adder 14 adds "0" and "1/3" and feeds back the sum "1/3" to accumulator 16. The first addition does not cause generation of a carry signal. In the second addition, "1/3" in accumulator 16 is added to "1/3" in scale register 15, so that the resultant sum is "2/3". As is apparent from the resultant sum, no carry signal is generated. In the third addition, "2/3" in the accumulator 16 is added to "1/3" in scale register 15, and the resultant sum is "1". In this case, a carry from the decimal part to the integer part occurs, and a significant carry signal is output. Since the addition result represents "1" (="3/3"), the decimal part is "0", and "0" is set again in accumulator 16. The above operations are then repeated. When the scale is set to be 1/3, adder 14 generates a significant (logic "1") carry signal "1" for every three additions. More specifically, adder 14 sequentially generates logic "0", logic "0", logic "1", logic "0", logic "0", logic "1", etc. In the first addition output from adder 14, a carry signal of logic "0" is supplied to AND gate 1, and at the same time a reduction mode signal of logic "1" is supplied to AND gate 1. The reduction mode signal of logic "1" is also supplied to OR gate 4. OR gate 4 continuously supplies signals of high level to AND gate 6, and thus AND gate 6 supplies the shift signal to source shift register 11 in response to the clock signal. Register 11 outputs 1bit at a time of an image dot pattern in response to the clock signal. Data generator 12 ORs the 1bit output with the most significant fit (MSB) of register 11, and supplies the OR product to register 13. Register 13 stores the OR product and feeds it back to generator 12. The above operation is repeated in correspondence with the clock signal.
At the same time AND gate 1 receives a carry signal of logic "0", and AND Gate 5 does not supply the shift signal to destination register 13 since the signal output from OR gate 3 is set at logic "0". In the second addition, no carry occurs from the decimal part to the integer part, and the same operation as in the first addition is performed. In the third addition, a significant (logic "1") carry signal is output from adder 14. The carry signal of logic "1" is supplied to AND gate 5 through OR gate 3. AND gate 5 supplies the shift signal (i.e., the carry signal of logic "1") to destination register 13 at the clock signal, and the contents of register 13 are shifted by one bit. In this state, a 3bit image dot pattern from register 11 is logically ORed with each other by generator 12, and the result is held as the MSB of register 13. In this manner, the above operations are repeated to reduce the image data by 1/3.
In the enlargement mode, an enlargement signal of logic "1" is supplied to AND gate 2 and OR gate 3. OR gate 3 outputs a signal of logic "1" so that AND gate 5 supplies a clock signal to destination register 13. Register 13 performs shifting in correspondence with the clock signal. In the first addition, since the carry signal is set at logic "0", AND gate 2 generates this signal, i.e., a logic "0". The signal of logic "0" is supplied to AND gate 6 through OR gate 4, and AND gate 6 does not supply the clock signal to source register 11. Information is not shifted through register 11. An image dot from register 11 is supplied to data generator 12, and generator 12 supplies its data to register 13. The same operation as in the first addition is repeated in the second addition. In the third addition, since the carry signal of logic "1" is output, this signal is supplied to register 11 through AND gate 2, OR gate 4, and AND gate 6. As a result, register 11 is shifted by one bit, and the next image dot pattern is generated. In the case of 3× enlargement, register 13 is shifted three times while register 11 is shifted once. Therefore, the same image dot from register 11 is copied in register 13 three times.
As is apparent from the above description, reduction or enlargement in units of dots is performed in the conventional image size converter. For this reason, in industrial fields requiring highspeed image size conversion, e.g., in an image retrieval system connected to an optical disk, a long waiting time is required for an operator since the processing speed is very low.
It is an object of the present invention to provide an image size converter for performing image size reduction or enlargement of a plurality of parallel bits.
In order to achieve the above object of the present invention, there is provided an image size converter, for enlarging or reducing the image size in accordance with a scale value, comprising:
means for inputting the scale value to the image size converter;
means in response to the scale value for generating in parallel a plurality of carry signals;
means in response to the parallel output of the plurality of carry signals and to the input image size conversion object dot pattern data for producing an output dot pattern converted in accordance with the scale value.
Other objects and features of the present invention will be apparent from the following description taken in connection with the accompanying drawings, in which:
FIG. 1 is a block diagram of a conventional image size converter;
FIG. 2 is a block diagram of an image size reduction circuit as an image size converter according to a preferred embodiment of the present invention;
FIG. 3 is a detailed logic diagram of the reduced data generator 42 in FIG. 2;
FIG. 4 is a table of thenumberofcarries encoding circuit 41, showing conversion between the bit pattern of the carry signals and the code of the number of carry signals;
FIG. 5 is a logic diagram showing the detailed arrangement of output data register 43 in FIG. 2;
FIG. 6 is a logic diagram showinq the detailed arrangement of the zone position generator 45 in FIG. 2;
FIG. 7 is a logic diagram of the selector 44 in FIG. 2;
FIGS. 8A through 8C are diagrams for explaining the operation of the image size reduction circuit in FIG. 2;
FIG. 9 is a block diagram of an image size enlargement circuit as the image size converter according to another preferred embodiment of the present invention;
FIG. 10 is a logic diagram showing the detailed arrangement of input data register 71 in FIG. 9;
FIG. 11 is a detailed logic diagram of the selector 73 in FIG. 9; and
FIGS. 12A through 12D are diagrams for explaining the operation of the image size enlargement circuit in FIG. 9.
FIG. 2 is a block diagram of an image size reduction circuit used as an image size converter according to a preferred embodiment of the present invention. In accordance with the present invention a parallel carry signal generator 38 is used in place of a serial carry signal thereby allowing faster image size conversion. In this embodiment, first through fourth additions of scale values and accumulation values are simultaneously performed, although the number of additions does not limit the scope of the invention. Each of adders 21 through 24 has inputs A and B and adds data signals input to inputs A and B. Adders 21 through 23 generate 1bit outputs of the integer parts (i.e., the lower bit of each integer part), and adder 24 generates a onebit output of the integer part, and a 16bit output as a decimal part. Accumulator 25 holds the 16bit decimal part from adder 24. An accumulated value from accumulator 25 is commonly supplied to inputs A of adders 21 through 24. Scale register 31 comprises a 16bit register for storing a designated reduction ratio. The reduction ratio is supplied from register 31 to input B of adder 21 and to 2X, 3X, and 4X value generators 32, 33, and 34. Generator 32 comprises a register in this embodiment. A value obtained by shifting the value of register 31 by one bit to the left is set in generator 32. Generator 33 comprises a register and adder. A value obtained by adding a scale register value to the 2X value shifted by one bit to the left is set in generator 33. A value obtained by shifting the scale register value by 2 bits to the left is set in generator 34. An output (2Δ) from generator 32 is input to input B of adder 22. An output (3Δ) from generator 33 is supplied to input B of adder 23. An output (4Δ) from generator 34 is supplied to input B of adder 24.
Exclusive OR gate 35 detects a noncoincidence between one bit of the integral part from adder 21 and one bit of the integral part from adder 22. Exclusive OR gate 36 detects a noncoincidence between one bit of the integral part from adder 22 and one bit of the integer part from adder 23. Exclusive OR gate 37 detects a noncoincidence between a bit of the integer from adder 23 and one bit of the integral part of adder 24.
Image size reduction data generator 40 comprises reduced data generator 42, thenumberofcarries encoding circuit 41, output data register 43, zone position generator 45, and selector 44. Generator 40 receives 4bit input data (i.e., an image size conversion object dot pattern) and determines correspondence (described below) between the 4bit input data and output data on the basis of the one bit of the integer part C0 from adder 21 and the output signals (i.e., carry signals C1 through C3) from exclusive OR gates 35, 36 and 37. Encoding circuit 41 encodes carry signals C0 through C3 and generates a 3bit carry code representing the number of carry signals. Generator 42 reduces the 4bit input data responsive to the input of carry signals C0 through C3 and generates reduced data having a maximum of 4 bits. Register 43 comprises, as here embodied, an 11bit register and holds output data from generator 42. The 7th through 10th bits of data from register 43 are used as input bits for output data from generator 42. The 0th through 6th bits of register 43 are used as output bits to selector 44. Register 43 has a barrel shift function having a maximum shift number of 4 bits. Before the output data from generator 42 is input to register 43, register 43 barrel shifts the storage contents by the number of carry signals represented by the code generated by encoding circuit 41.
The 7th bit of the output data register is fed back to reduction data generator 42 and is logically ORed with the next output data pattern.
Selector 44 selects four succeeding bits (e.g., 03, 14, 25, or 36) among the data stored in output data register 43 and outputs the selected bits. The selection of the 4bit data is based on the output of zone position generator 45 which generates zone position information (2 bits) representing a zone position (zone 0 of 03, zone 1 of 14, zone 2 of 25, or zone 3 of 36) on the basis of the code of the number of carry signals generated by encoding circuit 41.
FIG. 3 is a detailed logic diagram of the reduced data generator 42 shown in FIG. 2. The generator components which are not directly associated with the present invention are partially omitted. Referring to FIG. 3, generator 42 comprises programmable logic array 47, first OR gates 49, and second OR gate 51. Programmable array logic (RPAL) 47 receives input data to be reduced on input line 53. Carry signals C0 through C3 are supplied through input line 55. A shift amount is supplied to RPAL 47 through line 57. A desired mode is set through line 59. There are two ways of mode setting: one is simple extraction (i.e., if the carry signal extracts only the image dot corresponding to logic "1"); and the other is an OR calculation. RPAL 47 is programmed to reduce the input data according to the carry signal. An example of such a program is given later.
First OR gates 49 and second OR gate 51 are additional circuits for modifying the function which is not programmed by RPAL 47.
Feedback from bit 7 of output register 43 to reduced data generator 42 is executed by the program in RPAL 47 in the diagram of FIG. 3.
Thenumberofcarries encoding circuit 41 in FIG. 3 can preferably embody a readonly memory. As shown in FIG. 4, encoding circuit 41 receives a 4bit carry signal add has a conversion table for generating a code representing the number of carry signals of logic "1".
Output data register 43 in FIG. 2 comprises two programmable array logics (PALs) 61 and 63, as shown in FIG. 5. PALs 61 and 63 are programmed to shift the contents thereof by a designated shift amount, and its program is shown below.
__________________________________________________________________________PAL20R4A PAL DESIGN SPECIFICATIONDC0497P003A 1985 NOV. 29 Y. HAMADAREDUCE PALTOSHIBA JAPAN__________________________________________________________________________S10MHZ SRDD3 SRDD2 SRDD1 SRDD0 ORCA3 ORCA2 ORCA1 /ORD3RDCAO RDCA1 GND /OE RDCA2 /HLDCXE RDCA1D /REDD0 /REDD1/REDD2 /REDD3 SFT1 SFT0 CORMX VCC__________________________________________________________________________REDD3 : = ORD3 */HLDCXE + SRDD1 * /RDCA0 * /RDCA1 ORCA2*/HLDCXE+ SRDD0 * /RDCA0 * /RDCA1 * /RDCA2 * ORCA3*/HLDCXE+ RDCA1D * /SFT1 * /SFT0 * REDD3 * CORMX */HLDCXE+ RDCA1D * /SFT1 * SFTO * REDD2 * CORMX */HLDCXE+ RDCA1D * SFT1 * /SFT0 * REDD1 * CORMX */HLDCXE+ RDCA1D * SFT1 * SFT0 * REDD0 * CORMX */HLDCXE + HLDCXE * REDD3REDD2 : = SRDD2 * RDCA0 * ORCA1*/HLDCXE + SRDD1 * /RDCA0 * RDCA1 * ORCA2*/HLDCXE + SRDD1 * RDCA0 * /RDCA1 * ORCA2*/HLDCXE+ SRDD0 * /RDCAO * /RDCA1 * RDCA2 * ORCA3*/HLDCXE+ SRDD0 * /RDCA0 * RDCA1 * /RDCA2 * ORCA3*/HLDCXE+ SRDD0 * RDCA0 * /RDCA1 * /RDCA2 * ORCA3*/HLDCXE + HLDCXE * REDD2REDD1 : = SRDD1* RDCA0 * RDCA1 ORCA2*/HLDCXE + SRDD0 * /RDCA0 * RDCA1 * RDCA2 * ORCA3*/HLDCXE + SRDD0 * RDCA0 * /RDCA1 * RDCA2 * ORCA3*/HLDCXE + SRDD0 * RDCAO * RDCA1 * /RDCA2 * ORCA3*/HLDCXE + HLDCXE * REDD1REDD0 : = SRDD0 * RDCA0 * RDCA1 * RDCA2 * ORCA3*/HLDCXE + HLDCXE * RED00__________________________________________________________________________
Each output from PAL 61 corresponds to bit 3 through bit 6 of output register 43 in FIG. 2. Each output from PAL 63 corresponds to bit 0 through bit 2 of output register 43 in FIG. 2.
The logic diagram of the zone position generator 45 is shown in FIG. 6. Zone position generator 45 comprises adder 65 for adding the codes each representing the number of carry signals input and shift register 67 for holding an accumulated value of outputs from adder 65.
Selector 44 in FIG. 2 comprises a programmable array logic shown in FIG. 7. The programmable array logic is programmed to select four succeeding bits of the six bits output from output register 43 on the basis of zone position information supplied from zone position generator 45. The program is shown below:
__________________________________________________________________________PAL16R4 PAL DESIGN SPECIFICATIONDC0476P005A 1985 NOV. 29 Y. HAMADA4 BIT SHIFT PALTOSHIBA JAPAN__________________________________________________________________________S10MHZ /REDD3 /REDD2 /REDD1 /REDD0 NC SFT2 SFT1, SFT0GND /OE /Y0 /Y1 /XRD3 /XRD2 /XRD1 /XRD0 /Y2 /63 VCC__________________________________________________________________________XRD3 : = REDD3 * SFT2 * /SFT1 * /SFT0 + XRD3 * /SFT2 * /SFT1 * /SFT0 + XRD2 * /SFT2 * /SFT1 * SFT0 + XRD1 * /SFT2 * /SFT1 * /SFT0 + XRD0 * /SFT2 * SFT1 * SFT0XRD2 : = REDD2 * SFT2 * /SFT1 * /SFT0 + REDD3 * /SFT2 * SFT1 * SFT0 + XRD2 * /SFT2 * /SFT1 * /SFT0 + XRD1 * /SFT2 * /SFT1 * SFT0 + XRD0 * /SFT2 * SFT1 * /SFT0XRD1 : = REDD1 * SFT2 * /SFT1 * /SFT0 + REDD3 * /SFT2 * SFT1 * /SFT0 + REDD2 * /SFT2 * SFT1 * SFT0 + XRD1 * /SFT2 * /SFT1 * /SFT0 + XRD0 * /SFT2 * /SFT1 * SFT0XRD0 : = REDD0 * SFT2 * /SFT1 * /SFT0 + REDD3 * /SFT2 * /SFT1 * SFT0 + REDD2 * /SFT2 * SFT1 * /SFT0 + REDD1 * /SFT2 * SFT1 * SFT0 + XRD0 * /SFT2 * /SFT1 * /SFT0__________________________________________________________________________
The operation of the invention in accordance with the embodiment in FIG. 1 will be described with reference to FIG. and FIGS. 8A through 8C when a reduction ratio of 1/3 is used. In the circuit of FIG. 2, tree steps are repeated for 1/3 reduction processing.
Step 1
In step 1 adder 21 adds the contents of scale register 31 and of accumulator 25 which are in the initial state 1/3 and 0 respectively. Adder 22 adds the output from 2 Δ value generator and the contents of accumulator 25 which are in the initial state 2/3 and 0 respectively. Adder 23 adds the output from 3Δ value generator 33 and the contents of accumulator 25 which are 1 and 0 respectively. Adder 24 adds the output from 4Δ value generator 34 and the contents of accumulator 25. In the initial state the respective values are 4/3 and 0. In step 1, since X=0 in accumulator 25, the sums of adders 21, 22, 23 and 24 are 1/3, 2/3, 1, and 4/3, respectively. The decimal part of the sum from adder 24 is 1/3. The decimal part from adder 24 is held by accumulator 25 in response to the clock signal. As a result, the contents of accumulator 25 are updated from "0" to "1/3".
Exclusive OR gate 35 detects a coincidence or noncoincidence between 1bit portions of the integer parts of the sums from adders 21 and 22. If a coincidence is detected, exclusive OR gate 35 generates carry signal C1 of logic "0". Otherwise, exclusive OR gate 35 generates signal C1 of logic "1". Similarly, exclusive OR gate 36 detects a coincidence or noncoincidence between onebit portions of the integer parts of the sums from adders 22 and 23. If a coincidence is detected, exclusive OR gate 36 generates carry signal C2 of logic "0". Otherwise exclusive OR gate 36 generates signal C1 of logic "1". Exclusive OR gate 37 detects a coincidence or noncoincidence between onebit portions of the sums from adders 23 and 24. If a coincidence is detected, exclusive OR gate 37 generates carry signal C3 of logic "0". Otherwise, exclusive OR gate 37 generates signal C3 of logic "1".
The exclusive OR products of the sums from adders 21 through 24 are calculated for the following reason.
If the reduction ratio is 1/3, the pattern of the carry signals as image size conversion control signals is a pattern in which logic "1" appears for every two bits, i.e., a pattern of "0", "0", "1", "0", "0", "1", . . . However, the carry signals from adders 21 through 24 do not always coincide with the above bit pattern. For example, if the contents X of accumulator 25 is "0" and content of scale register 31 is "1/3", the sums from adders 21 through 24 are sequentially "1/3", "2/3", "3/3", and "4/3", and the logic levels of the corresponding carry signals are "0", "0", "1", and "1". The pattern of the carry signals does not coincide with the desired bit pattern. In order to prevent this, when a carry signal of logic "0" appears, the logic level of the immediately preceding carry signal is referenced. If the immediately preceding carry signal is set at logic "1", the subsequent carry signal is set at logic "0". For example, if the carry signal from adder 22 is set at logic "1" and the carry signal from adder 21 is also set at logic "1", the exclusive OR product of outputs from adders 21 and 22 is calculated to set the carry signal from OR gate 35 to be logic "0". The output of logic "0" is thus output as carry signal C1. Similarly, if the carry signals from adders 22 and 23 are set at logic "1", the carry signal from adder 23 is set at logic "0" and is output as carry signal C2. If the carry signals from adders 23 and 24 are set at logic "1", an exclusive OR product is calculated such that the carry signal from adder 24 is set at logic "0" and is output as carry signal C3.
As is apparent from the above description, carry signal C0 as one bit of the integer part from adder 21 and carry signals C1, C2, and C3 as outputs from exclusive OR gates 35 through 37 correspond to carry signals in the 4kth (where k=0, 1, 2, . . . ), (4k+1)th, (4k+2)th, and (4k+3)th additions in adder 14 of the conventional circuit of FIG. 1. According to this embodiment, the carry signals required for image size reduction can be generated at a rate four times that of the conventional circuit in FIG. 1.
In step 1, onebit portions of the integer parts of the sums from adders 21 through 24 are respectively "0", "0", "1", and "1". The logic levels of carry signals C0 through C3 are "0", "0", "1", and "0", as shown in the operation diagram of FIG. 8A. Signals C0 through C3 are supplied to reduced data generator 42. Generator 42 also receives 4bit input data (a reduction object input dot pattern) in response to a clock signal (not shown). Assume that four bits of input data from the MSB in step 1 are defined as I0, I1, I2, and I3. In this case, since logic levels of signals C0, C1, C2 and C3 are "0", "0", "1", and "0", generator 42 continuously reduces the image size of the dot pattern until the carry signal of logic "1" appears, i.e., up to the position of input bit I2. In accordance with this invention, two types of techniques are available to reduce the image size. One is a technique for validating only the dot corresponding to the carry signal of logic "1" and invalidating dots corresponding to carry signals of logic "0". The other is a technique for calculating an OR product of dot patterns until the carry signal of logic "1" appears and employing the OR output as a dot pattern for each image size reduction cycle. However, in this embodiment, for the sake of simplicity, the technique for calculating the OR product will be described. Reduced data generator 42 calculates an OR product of bits I0 through I2. The OR product is stored at the 7th bit position of output data register 43, as shown in FIG. 8A, provided that the start output bit is given as 00. Bit I3 is stored at the 8th bit position of register 43, as shown in FIG. 8A, and serves as output bit 01(*) to be reduced next.
Carry signals C0 through C3 are supplied to thenumberofcarries encoding circuit 41. Encoding circuit 41 encodes signals C0 through C3 and generates a 3bit code representing the number of significant carry signals as shown in FIG. 4 (i.e., the number of carry signals of logic "1"). In step 1 wherein signals C0, Cl, C2, and C3 are respectively "0", "0", "1", and "0", the code of the number of carry signals is given as "001". This code is supplied to output data register 43. Register 43 performs barrel shifting by a value represented by the code from encoding circuit 41. As a result, 00 and 01(*) at the 7th and 8th bit positions of register 43 are shifted to the 6th and 7th bit positions, as indicated by arrow A in FIG. 8A.
The code from thenumberofcarries encoding circuit 41 is also supplied to zone position generator 45. Generator 45 accumulates the codes. An accumulated result is used to count the number of cycles for outputting signals from reduced data generator 42 to output data register 43. When the accumulated result represents 4 times or cycles, i.e., the output is sent from generator 42 to register 43 four times, the MSB of the 3bit sum is set at logic "1" (however, the MSB is not set at logic "1" in step 1). When the MSB of the 3bit sum is set at logic "1", it indicates that an output dot pattern of 4 or more bits is present in output register 43. Zone position generator 45 supplies the lower 2 bits of the accumulated value as zone position information to selector 44. If zone position information is "00", it indicates a zone of the 3rd through 6th bits of output data register 43. If information is "01", it indicates a zone of the 2nd and if "11", a zone of the 0th through 3rd bits.
Step 2
In step 2, since the content X of accumulator 25 is 1/3, the sums from adders 21 through 24 are respectively "2/3", "3/3", "4/3", and "5/3". The logic levels of onebit portions of the integer parts of the sums are respectively "0", "1", "1", and "1". The logic levels of carry signals C0, C1, C2, and C3 are "0", "1", "0", and "0". In this case, the decimal part of the sum from adder 24 is "2/3". Therefore, content X of accumulator 25 is updated from "1/3", to "2/3".
Referring to FIG. 8B, if the bits from the start bit of input data (4 bits) in step 2 are defined as I4, I5, I6, and I7, reduced data generator 42 calculates an OR product of a nonreduced "01(*)" held at the 7th bit position of register 43, I4, and I5 since the logic levels of carry signals C0, C1, C2, and C3 are respectively "0", "1", "0", and "0". The OR product is stored as nonreduced output bit "01" at the 7th bit position of output data register 43, as shown in FIG. 8B. Reduced data generator 42 calculates an OR product of I6 and I7. The OR result is stored as nonreduced output bit 02(*) at the 8th bit position of output data register 43, as shown in FIG. 8B.
Register 43 performs parallel shifting by the number of carry signals of logic "1" represented by the code in the same manner as in step 1. In step 2 where logic levels of carry signals C0, C1, C2, and C3 are respectively "0", "1", "0", and "0", the code is "001". Barrel shifting is performed in step 2. Bits 00, 01 and 02(*) at the 6th, 7th, and 8th bit positions of register 43 are shifted to the 5th, 6th, and 7th positions, as indicated by arrow B in FIG. 8B, respectively. An accumulated value (3 bits) of codes representing the numbers of 2bit carry signals in zone position generator 45 is given as "010".
Step 3
In step 3, since the contents X of accumulator 25 is 2/3, the sums of adders 21, 22, 23 and 24 are "3/3", "4/3", "5/3", and "6/3", respectively. The logic levels of onebit portions of the sums are "1", "1", "0", and "0", and the logic levels of carry signals C0, C1, C2, and C3 are "1", "0", "0", and "1", respectively. The decimal part of the sum from adder 24 is "0". Therefore, contents X of accumulator 25 is updated from "2/3" to "0".
Assume bits from the start bit of input data (4 bits) in step 3 are given as I8, I9, I10, and Ill, respectively, as shown in FIG. 8C. Since logic levels of carry signals C0 through C3 are respectively "1", "0", "0", and "1" in this case, reduced data generator 42 calculates an OR product of nonreduced bit 02(*) held at the 7th bit position of output data register 43 and input bit I8. This OR product is stored as nonreduced output bit O2 at the 7th bit position of register 43, as shown in FIG. 8C. Generator 42 calculates an OR product of I9 through Ill. This OR product is stored as nonreduced output bit 03 at the 8th bit position of register 43, as shown in FIG. 8C.
In output data register 43, barrel shifting is performed on the basis of the number represented by the code in the same manner as in step 1. In step 3 the logic levels of carry signals C0 through C3 are respectively "1", "0", "0", and "1", the code of the number of carry signals of logic "1" is "010" (FIG. 4). Therefore, 2bit barrel shifting is performed in step 3. Bits 00, 01, 02, and 03 at the 5th, 6th, 7th, and 8th bit positions of output data register 43 are shifted to the 3rd, 4th, 5th, and 6th bit positions, as indicated by arrow C in FIG. 8C.
In step 3, zone position generator 45 adds code "010" to the accumulated code value "010" representing the number of 2bit carry signals obtained up to step 2. The 3bit sum calculated by generator 45 is "100". When the MSB of the 3bit sum in step 3 is "1", generator 45 supplies the lower two bits of the sum as zone position information to selector 44. Selector 44 selects four output bits from the zone position of data register 43 on the basis of the zone position information. The selected bits constitute output data. Since the zone position information is "00" in this case, the contents of the 3rd through 6th bits of output data register 43, i.e., 00 through 03, are selected.
In step 3, the contents X of accumulator 25 is updated from "2/3" to "0" (i.e., the initial value). Therefore, in 1/3 reduction processing by the circuit in FIG. 2, the operations in steps 1 through 3 are repeatedly performed for 4bit input data.
In the above embodiment, since 2bit reduced data is supplied from reduced data generator 42 to output register 43, the pieces of reduced data are packed in units of four bits, and 4bit reduced data is output from selector 44. For this purpose, the circuit includes thenumberofcarries encoding circuit 41, output register 43, zone position generator 45, and selector 44. However, the present invention can be realized without using these components.
For the sake of simplicity, in the above embodiment, reduced data generator 42, output data register 43, and selector 44 are operated in the same step on the basis of the same carry signals C0 through C3. However, as is apparent from the circuit in FIG. 1, pipeline processing can also be performed.
FIG. 9 is a block diagram showing a second preferred embodiment of the present invention. The same reference numerals as in FIG. 2 denote the same parts of the image size converter of FIG. 9. The circuit in FIG. 9 is an image size enlargement circuit. Scale register 31 stores scale values as inverse numbers of enlargement ratios in place of reduction ratios.
Enlargement data generator 70 receives 4bit input data and determines the correspondence between bit 1 through 4 of the 4bit input data and 4bit output data on the basis of carry signals C0 through C3. Input data register 71 stores 4bit input data in response to a clock signal. Register 71 comprises two 4bit registers and has a function of 4bit shifting. If seven bits from the upper bits, excluding the MSB of input data register 71, are given as 0th, 1st, . . . 6th bits, the 0th through 2nd bits are used only for outputs to the next stage, and the 3rd through 6th bits are used for an input zone of the 4bit input data and an output zone for the next stage. Selector 73 selects four succeeding bits of the data (i.e., the 0th through 6th bits) from input data register 71.
Thenumberofcarries encoding circuit 41 has the same arrangement as that in FIG. 2. Encoding circuit 41 in FIG. 9 encodes carry signals C0 through C3 and generates a 3bit code representing the number of carry signals of logic "1".
Zone position generator 45 has the same arrangement as that in FIG. 2. Generator 45 in FIG. 9 generates zone position information (2 bits) representing a zone position of register 71 which includes 4bit data to be selected by selector 73. The zone position information is generated on the basis of the code generated by encoding circuit 41. If the zone position information is "01", then it represents a zone of the 0th through 3rd bits of input data register 71; if "10", then a zone of the 1st through 4th bits; if "11", then a zone of the 2nd through 5th bits; and if "00", a zone of 3rd through 6th bits. Enlargement data generator 75 uses 4bit data selected by selector 73 and generates 4bit output data enlarged on the basis of the carry signals.
Input data register 71, in FIG. 9 comprises first and second shift registers 77 and 79, as shown in FIG. 10. Selector 73 and enlargement data generator 75 in FIG. 9 comprise programmable array logics (PALs), respectively, as shown in FIG. 11. PAL 73 is programmed to receive 6bit information from input register 71 and output 4bit information of a designated zone to generator 75 on the basis of zone position information supplied from zone position generator 45. Enlargement data generator 75 is programmed to enlarge 4bit dot pattern data from selector 73 on the basis of carry signals C0 through C3.
The operation of the circuit in FIG. 9 will be described with reference to FIGS. 12A through 12D when the enlargement ratio is 3/1.
The scale value used is an inverse number of the enlargement ratio; thus 1/3 is the scale value which is the same as in the first embodiment. Carry signals C0 through C3 recur in an order of "0", "0", "1", "0"; "0", "1", "0", "0"; and "1", "0", "0", "1". Therefore, 3×enlargement processing can be achieved by repeating the three steps described below.
Step 1
Assume that 4bit input data is input to input data register 71 in step 1. The bits from the start bit of this input data are respectively defined as I0, Il, I2, and I3. Bits I0 through I3 are respectively stored at the 3rd through 6th bit positions of register 71, as shown in FIG. 12A.
In step 1, the logic levels of carry signals C0, Cl, C2, and C3 are respectively "0", "0", "1", and "0" in the same manner as in the first embodiment. Signals C0 through C3 are supplied to thenumberofcarries encoding circuit 41. Encoding circuit 41 encodes the carry signals and generates a 3bit code representing the number of carry signals of logic "1" in the same manner as in encoding circuit 41 of FIG. 2. In step 1 wherein the logic levels of carry signals C0, Cl, C2, and C3 are respectively "0", "0", "1", and "0", the code is "001" (FIG. 4). The code is also supplied to zone position generator 45. Generator 45 adds the code to an accumulated value ("000" in this case) of codes. The lower two bits of the 3bit sum from generator 45 are used as zone position information. Therefore, in step 1, accumulated value "00" is supplied as zone position information to selector 73.
If the zone position information from zone position generator 45 is "00", selector 73 selects the contents of the 3rd through 6th bits of input data register 71, i.e., input bits I0 through I3 from the 0th through 3rd bits of selector 73. The selected bits are sent to enlargement data generator 75, as shown in FIG. 12A. Carry signals C0 through C3 are supplied to generator 75. Dots of input data are copied by generator 75 until a carry signal of logic "1" appears. More specifically, since the logic levels of carry signals C0 through C3 are respectively "0", "0", "1", and "0", each dot of the input data is copied three times. In this case, start input bit I0 is output as output bits 00 through 02 from the 0th through 2nd bits of generator 75. The next input bit Il is output as output bit 03 from the 3rd bit position of generator 75.
Step 2
When enlargement processing of start bit I0 of 4bit data in step 1 is completed, remaining bits Il through I3 are shifted by 4 bits to the 0th through 2nd bits of input data register 71. Therefore, subsequent 4bit input data is stored at the 3rd through 6th bit positions. In this case, this input data consists of I4 through I7.
In step 2, the logic levels of carry signals C0, Cl, C2, and C3 are respectively "0", "1", "0", and "0" in the same manner as in step 2 of the first embodiment. In this case, the code generated by encoding circuit 41 is "001" (FIG. 4). Zone position generator 45 adds code "001" to the accumulated value "01" of codes representing the numbers of carry signals of logic "1" calculated up to step 1. The accumulated value "10" as the lower two bits of the 3bit sum is used as zone position information in the next step, i.e., step 3. In step 2, accumulated value "01" up to step 1 is supplied as zone position information to selector 73.
If zone position information from zone position generator 45 is "01", the contents, i.e., input bits Il through I4 are output from the 0th through 3rd bits of selector 73. Input bits Il through I4 are input to enlargement data generator 75, as shown in FIG. 12B. Since the logic levels of carry signals C0 through C3 are respectively "0", "1", "0", and "0", generator 75 copies input dot Il up to the lst bit (the output bit 05 position in this case) of 4bit output data. Generator 75 generates start input bit Il as output bits 04 and 05 from the 0th and 1st bit positions thereof and the next input bit I2 as output bits 06 and 07 from the 2nd and 3rd bit positions.
Step 3
In step 3, the logic levels of carry signals C0, Cl, C2 and C3 are respectively "1", "0", "0", and "1". In this case, a code generated by thenumberofcarries encoding circuit 41 is "010". Zone position generator 45 adds code "010" to accumulated value "010" counted up to step 2. The lower two bits "00" of the resultant sum "100" are used as zone position information in step 4. In step 3, value "10" accumulated up to step 2 is supplied as zone position information to selector 73.
If zone position information from zone position generator 45 is "10", selector 73 selects the contents of the 1st through 4th bits of input data register 71, i.e., input bits I2 through I5 from the 0th through 3rd bit positions and outputs the selected bits to enlargement data generator 75, as shown in FIG. 12C. If the logic levels of carry signals C0 through C3 are respectively "1", "0", "0", and "1", generator 75 copies input dot I2 up to the 0th position (the position of output bit 08 in this case) of 4bit output data. Generator 75 then copies input data I3 up to the 3rd bit position (position of output bit 08 in this case). In this case, generator 75 outputs start input bit I2 as output bit 08 from its 0th bit position, and the next input bit I3 as output bits 09 through 011 from its 1st through 3rd bit positions.
Step 4
Since the logic levels of the carry signals C0 through C3 are respectively "0", "0", "1", and "0" in the same manner as in step 1 a code representing the number of carry signals of logic "1" is "001". Value "00" of accumulated codes representing the numbers of carry signals of logic "1" is updated to be "001" in zone position generator 45. Updated value "01" is used as zone position information in step 5. In step 4, value "00" as a result of accumulation up to step 3 is supplied as zone position information to selector 73.
If zone position information from zone position generator 45 is "0", selector 73 selects the contents of the 3rd through 6th bit positions of input data register 71, i.e., input bits I4 through I7 in this case, from the 0th through 3rd bit positions of selector 72. The selected bits are output to enlargement data generator 75, as shown in FIG. 12D. When the logic levels of carry signals C0 through C3 are respectively "0", "0", "1", and "0", generator 75 outputs start input bit I4 as output bits 012 through 014 from the 0th through 2nd bits thereof. The next input bit I5 is set as output bit 015 at the 3rd bit position of generator 75. Enlargement processing in step 4 is the same as that in step 1.
When enlargement processing of start bit I4 of the 4bit input data is completed, remaining input bits I5 through I7 are shifted by four bits to the 0th through 2nd bit positions of input data register 71. The following 4bit input data is stored in the 3rd through 6th bit positions, and the same operation as in step 2 is performed. Processing in step 6 and subsequent steps is the same as described above. 3× enlargement is repeated in units of 3 steps.
In the embodiments of FIGS. 2 and 9, the onebit portion of the integer part of the sum from adder 21 is given as carry signal C0. However, a carry from the decimal part of the sum from adder 21 to the integer part may be used as carry signal C0.
The decimal part of the sum from adder 24 is stored in accumulator 25 in FIG. 2. However, a sum including the integer part may be stored in accumulator 25. In this case, signal lines must be connected such that only the decimal part of the contents of accumulator 25 is supplied to input A of adder 21. All contents, i.e., both the integer and decimal parts of accumulator 25, may be supplied to inputs A of adders 22 through 24.
Furthermore, when the sum, including the integer part from adder 24, is stored in accumulator 25 as shown in FIGS. 2 and 9, the onebit portion of the integer part (if the integer part consists of a plurality of bits, the onebit portion is the least significant bit (LSB) among the contents of accumulator 25 and the onebit portion of the integer part (if the interger part consists of a plurality of bits, the onebit portion is the LSB) of the sum from adder 21 are calculated by an exclusive OR gate, and an output signal from the gate may be used as carry signal C0. In this case, both the integer and decimal parts as contents of accumulator 25 may be input to input A of adder 21.
In each of the embodiments described above, exclusive 0R gate 35 is used to produce, e.g., carry signal Cl. However, a comparator may be used in place of the exclusive OR gate. In this case, if the integer part of the sum from adder 22 consists of a plurality of bits, a noncoincidence of the integer part may be detected.
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Cited By (19)
Publication number  Priority date  Publication date  Assignee  Title 

US5020115A (en) *  19890710  19910528  Imnet Corporation  Methods and apparatus for dynamically scaling images 
US5097518A (en) *  19900227  19920317  Eastman Kodak Company  Technique for performing digital image scaling by logically combining or replicating pixels in blocks of differing groupsizes 
US5107255A (en) *  19881115  19920421  Sharp Kabushiki Kaisha  Control device for a display apparatus 
US5140648A (en) *  19891228  19920818  Eastman Kodak Company  Scaler gate array for scaling image data 
US5265176A (en) *  19910417  19931123  HewlettPackard Company  Method and apparatus for mapping printer resolution using lockuptables 
WO1994010643A1 (en) *  19921102  19940511  The 3Do Company  Improved method and apparatus for processing image data 
US5335295A (en) *  19910508  19940802  International Business Machines Corporation  System and method for scaling a digital image 
US5345542A (en) *  19910627  19940906  At&T Bell Laboratories  Proportional replication mapping system 
US5365602A (en) *  19910823  19941115  Levien Raphael L  Integrated halftone screening and enlarging using an enlargement mapping pattern having linked, unique pattern segments 
US5400051A (en) *  19921112  19950321  International Business Machines Corporation  Method and system for generating variably scaled digital images 
US5493420A (en) *  19890220  19960220  Hitachi, Ltd.  Dot density conversion method and system 
US5572235A (en) *  19921102  19961105  The 3Do Company  Method and apparatus for processing image data 
FR2738651A1 (en) *  19950913  19970314  Odeum Microsystems Inc  sampling of frequency conversion system 
US5638467A (en) *  19930514  19970610  Industrial Technology Research Institute  Bitreversing method and system for linear image scaling 
US5706369A (en) *  19950531  19980106  Rockwell International Corporation  Basen resolution converter 
US5729357A (en) *  19890802  19980317  Canon Kabushiki Kaisha  Image processing apparatus 
US5774110A (en) *  19940104  19980630  Edelson; Steven D.  Filter RAMDAC with hardware 11/2D zoom function 
US6370281B1 (en) *  19971201  20020409  Nec Corporation  Apparatus and method for detecting enlarging ratio or reducing ratio of image data 
US20150180666A1 (en) *  20120718  20150625  Nec Corporation  Universal hash function computing device, method and program 
Citations (8)
Publication number  Priority date  Publication date  Assignee  Title 

US4054914A (en) *  19751029  19771018  Olympus Optical Company Limited  Facsimile scanning conversion system 
US4468755A (en) *  19801031  19840828  Tokyo Shibaura Denki Kabushiki Kaisha  Document size conversion circuit for a document filing system 
US4532602A (en) *  19820308  19850730  The Mead Corporation  Device for electrical variable magnification of document image 
US4587621A (en) *  19820308  19860506  The Mead Corporation  Device for electrical variable magnification of document image 
US4672680A (en) *  19840619  19870609  The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland  Raster image manipulator 
US4712185A (en) *  19840428  19871208  Kabushiki Kaisha Toshiba  Dot interpolation control system 
US4736438A (en) *  19850123  19880405  U.S. Philips Corporation  Image processing device for the realtime processing and recognition of twodimensional images, and an image processing system including at least two seriesconnected image processing devices of this kind 
US4799173A (en) *  19860228  19890117  Digital Equipment Corporation  Transformation circuit to effect raster operations 
Patent Citations (8)
Publication number  Priority date  Publication date  Assignee  Title 

US4054914A (en) *  19751029  19771018  Olympus Optical Company Limited  Facsimile scanning conversion system 
US4468755A (en) *  19801031  19840828  Tokyo Shibaura Denki Kabushiki Kaisha  Document size conversion circuit for a document filing system 
US4532602A (en) *  19820308  19850730  The Mead Corporation  Device for electrical variable magnification of document image 
US4587621A (en) *  19820308  19860506  The Mead Corporation  Device for electrical variable magnification of document image 
US4712185A (en) *  19840428  19871208  Kabushiki Kaisha Toshiba  Dot interpolation control system 
US4672680A (en) *  19840619  19870609  The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland  Raster image manipulator 
US4736438A (en) *  19850123  19880405  U.S. Philips Corporation  Image processing device for the realtime processing and recognition of twodimensional images, and an image processing system including at least two seriesconnected image processing devices of this kind 
US4799173A (en) *  19860228  19890117  Digital Equipment Corporation  Transformation circuit to effect raster operations 
Cited By (20)
Publication number  Priority date  Publication date  Assignee  Title 

US5107255A (en) *  19881115  19920421  Sharp Kabushiki Kaisha  Control device for a display apparatus 
US5493420A (en) *  19890220  19960220  Hitachi, Ltd.  Dot density conversion method and system 
US5020115A (en) *  19890710  19910528  Imnet Corporation  Methods and apparatus for dynamically scaling images 
US5729357A (en) *  19890802  19980317  Canon Kabushiki Kaisha  Image processing apparatus 
US5140648A (en) *  19891228  19920818  Eastman Kodak Company  Scaler gate array for scaling image data 
US5097518A (en) *  19900227  19920317  Eastman Kodak Company  Technique for performing digital image scaling by logically combining or replicating pixels in blocks of differing groupsizes 
US5265176A (en) *  19910417  19931123  HewlettPackard Company  Method and apparatus for mapping printer resolution using lockuptables 
US5335295A (en) *  19910508  19940802  International Business Machines Corporation  System and method for scaling a digital image 
US5345542A (en) *  19910627  19940906  At&T Bell Laboratories  Proportional replication mapping system 
US5365602A (en) *  19910823  19941115  Levien Raphael L  Integrated halftone screening and enlarging using an enlargement mapping pattern having linked, unique pattern segments 
WO1994010643A1 (en) *  19921102  19940511  The 3Do Company  Improved method and apparatus for processing image data 
US5572235A (en) *  19921102  19961105  The 3Do Company  Method and apparatus for processing image data 
US5400051A (en) *  19921112  19950321  International Business Machines Corporation  Method and system for generating variably scaled digital images 
US5638467A (en) *  19930514  19970610  Industrial Technology Research Institute  Bitreversing method and system for linear image scaling 
US5774110A (en) *  19940104  19980630  Edelson; Steven D.  Filter RAMDAC with hardware 11/2D zoom function 
US5706369A (en) *  19950531  19980106  Rockwell International Corporation  Basen resolution converter 
FR2738651A1 (en) *  19950913  19970314  Odeum Microsystems Inc  sampling of frequency conversion system 
US6370281B1 (en) *  19971201  20020409  Nec Corporation  Apparatus and method for detecting enlarging ratio or reducing ratio of image data 
US20150180666A1 (en) *  20120718  20150625  Nec Corporation  Universal hash function computing device, method and program 
US9515830B2 (en) *  20120718  20161206  Nec Corporation  Universal hash function computing device, method and program 
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JP2509563B2 (en)  19960619  grant 
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