SU1259261A1 - Device for centralized controlling of computer system - Google Patents

Abstract

The invention can be used in the construction of control computing systems. The purpose of the invention is to increase the efficiency of use of equipment. The proposed device contains a control processor, a group of processors, a shaper, exchange nodes, and. two switches. The purpose of the invention is achieved by introducing two switches into the device, which allows to organize arbitrary interprocessor exchange and exchange with external devices. In addition, a memory block is introduced into the structure of the loop former, which makes it possible to significantly reduce hardware costs during the implementation of the loop former. 1 hp f-ly, 7 ill. C 9 (LU SP JUD

Description

The invention relates to computing technology and can be used to build high-performance multiprocessor computing systems designed for real-time data processing.

The purpose of the invention is to reduce equipment.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 shows an example of a control processor implementation scheme; in fig. 5 shows an example of a processor implementation; in fig. 4 is a block diagram of a loop former; in fig. 5 is an example of a switch implementation scheme; in fig. 6 is an example of an exchange node implementation scheme; in fig. 7 is a simplified flowchart of a computing system functioning algorithm.

The system contains (Fig. 1) the control processor 1, a group of processors 2 -2. ; shaper 3 cycles, nodes, exchanges, switch 5 external exchanges, switch 6 interprocessor exchanges, buses 7 and 8 control switches 5 and 6, tires 9 and 10 shaper control 3 cycles, output Innu 11 formers 3 cycles, tires 12-14 controlling a group of processors 2, inputs-outputs 15 of the device.

The control process 1 (Fig. 2) consists of a register of 16 commands, a block of 17 memory of micro-instructions addresses, a register of 18 addresses of micro-instructions, a block of 19 memory of micro-instructions, a register of 20 micro-instructions, a clock generator 21, an output 22 of a register of commands, a switch 23, a memory block 24, an adder 25, a general purpose register block 26, a 27 result result register and a micro-command decoder 28.

Each processor 2 contains (FIG. 3) a control block 29 containing a register 30 of the current command address, a command register 31, a microinstruction address memory block 32, a microcommand address register 33, a microinstruction memory block 34, a microinstruction register 35, a clock pulse generator 36 and a block 37 of adding, including a switch 38, a block 39 of memory, an adder 40, a block 41 of general purpose registers, a register 42 of result features, a state register 43, de0

five

20

25

thirty

35

40

45

50

55

44 microinstructor encoder, processor number depmfrarator 45 and switch 46, the State Register 43 contains three triggers: a flip-flop trigger, an exchange readiness trigger with external devices and a readiness trigger and interprocessor exchange.

The shaper 3 cycles contains (FIG. 4) an address counter 47, a memory block 48, a group of elements And 49, a comparison circuit 50, a clock counter 51, an And element 52, a clock pulse generator 53 and a trigger trigger 54.

Switches 5 and 6 have the same structure and contain 2n inputs and 2n outputs. The switches contain (FIG. 5) a group of elements OR 55, a matrix of multiplexers 56, a group of decoders 57, a group of registers 58, a group of memory blocks 59, a register 60, a decoder 61, and a register 62.

The exchange node contains (FIG. 6) an output register 63, a trigger 64, an input register 65, a trigger 66, input buses 67-69, and output buses 70-72.

The operation of the system is determined by the control programs: recorded in the memory block 24 of the control processor 1, and the exchange of information between the control processor 1 and the processor 2 is carried out on buses 12 and 13. For this, the control processor 1 on the bus 12 outputs the code number of the corresponding processor 2, which is decrypted by the decoder 45, which opens the switch 46 and organizes the exchange of information between the memory unit 39 of the corresponding processor 2 and the control processor 1 (memory unit 24) through bus 13.

The task cycle is set by the shaper of 3 cycles. When any of the processors 2 fails, the task solved on it to other processors is provided. This is done by the control processor by reloading programs and data into other processors (into memory blocks 39 of processors 2) on buses 12 and 13. This is how the problem solving cycle in healthy processors changes by writing and generating 3 cycles of new control processor codes one.

Switch 5 is intended for organizing the exchange between any of the processors 2 and exchange nodes 4, switch 6 is intended for organizing

arbitrary interprocessor exchanges.

The decoder 57 is designed to select one of the multiplexers 56 in the matrix column of the multiplexers, the register 58 and a group of memory blocks 59 are used to store the codes of the switching program. The loading and configuration of switches 5 and 6 is carried out by the control processor 1 via buses 7 and 8.

The loading of a group of memory blocks 59 by switching programs is carried out as follows. Bus 7. (8.) gives the code of memory block number 59, and bus 7 (8) gives the control switching code. If it is necessary to organize an exchange (the controlling processor 1 processor 2 is informed about this by installing the corresponding readiness for exchange in the state register 43 in the unit), the control processor 1 sets the required address to the register 60 via which (from a group of blocks) 59 memories are read corresponding control switch codes.

The device works as follows.

After turning on the computer system (Fig. 7), the control processor 1 sets to the initial state of the device and initializes the shaper of 3 cycles.

The loading is carried out as follows. Bus 9 on the meter

47 sets the first address block

48pam tee, bus 9 is sent

Equal code. The control code (Fig. 4) consists of three fields: the Q field is intended for storing the codes of the numbers of the processors 2 and contains n bits (equal to the number of processors 2, the unit in the i-th bit starts the i-th processor 2 via bus 11) ; the b field contains one bit and is intended to stop the shaper of 3 cycles after the completion of the problem solving loop formation; The b field is intended to store the binary codes of the operation cycles of the respective processors. In the first cell / block 48 of the box, all units are written in the Q field. During initial loading, it is loaded into memory block 48 only

go

15

20

25

35

ABOUT

B

50 55

2592614

one control code (first cell).

The initiation of the operation of the processor 2 takes place from the control processor 5 by sending a trigger signal via bus 9 to the shaper of 3 cycles, and the trigger 54 is set to one, the unit output of which allows the first control code from block 48 to pass through the group 49 memory and starts the generator 53. Single signals from the output of the generator 3 cycles on the bus 11 (a high potential is established in all bits of the bus) start the generators 36 cycles of all processors 2. Moreover, the registers 30 of the current address are all percent 2 is a quarrel zero address to which a block 39 of memory 2 write a text processor program and the after starting the generator 36 is accomplished its execution in the processor 2. Thus the cycle is started performing textual program processor 2.

Counters 51 clocks shaper 3 cycles starts counting pulses from the generator 53 pulses.

Comparison circuit 50 compares the contents of the 51 clock counter with the code in register 43 (field b). Binary code in the & corresponds to the time interval for execution of the text program in processor 2. A comparison pulse of these codes resets the counter 51 to the zero state and, via element 51 (recorded in field B 1) also resets the trigger 54, and additionally increments the contents of the counter 47 of the address. A single output of the trigger 54 (at the output zero potential) blocks the operation of the generator 53 and the second input of a group of elements 49, thus all potentials of the bus 11 are set to zero potentials and the operation of the generators 36 clocks of the processors 2 is blocked.

At the end of the test program in the processor 2, the corresponding sign is entered into the state register 43, and the single state of the trigger trigger corresponds to the operational state of the processor, zero to the non-functional state.

The test program termination signal is issued by the shaper 3 cyc30

from zero output (high potential) of trigger 54 via bus 10, which flows through switch 23 of control processor 1 to memory block 24, where it is analyzed by control processor 1. Next, the control processor analyzes the contents of register 43 of processor 2, for which, via the bus, through the switch 23 enters into the memory block 24. Having determined the number and numbers of healthy processors 2, the control processor 1 allocates resources and loads the processors 2 with programs and data as follows. Bus 12 provides processor number 2, which is decrypted by decoder 45, and switch 46 opens, and bus 13 loads processor memory 39. In addition, register 30 of the current instruction address of processor 2 is set in register 30 . Then, the shaper of 3 cycles is loaded, the cell address of the memory block 48 is assigned via the bus 9, and the control code via the bus 92. After the loading of the memory block 48 is completed, the initial address of the cell of the program for solving task cycles is recorded in the counter 47. Then, the control processor 1 starts the generator of 3 cycles to solve the problem. For this purpose, the trigger unit 54 is installed on the bus 9d. When solving the problem, the programs of the processors 2 provide for the points of dianosti

upon reaching which, in register 30, the current address of the instructions of the processors 2 is set to zero (the address of the test test program), and the 3-cycle generator performs the launch of the processors 2 to implement the test: program. At the end of the test I program, the comparison circuit 50 is triggered (1 is written in this control code field B) and the counter 51 is reset, the pulse generator 53 is blocked, the contents of counter 47 are incremented, and the trigger 54 is reset, the zero output of which notifies bus 10 control processor 1 on the completion of the test program. Next, the control processor 1 performs a processor health check, i.e. analyzes the state of the trigger register flush from the state of the processor 2. If all the processors 2 turned out to be operational, the control processor 1 triggers the shaper 3 cycles and, therefore, the processors 2 to continue the execution of the solved problem. When out of service

One or several processors 2, the control processor 1 performs the redistribution of resources and the restart of the processors 2 by programs and data, the shaper 3 cyclops - by new control, by their codes, and the switches - by the new corresponding switching codes. Next, the control processor 1 starts the shaper 3 cycles to continue execution

solvable problem.

If it is necessary to organize information exchange between the processors 2 and external devices, the control processor 1 analyzes the readiness of the processor 2 for the exchange according to the state of the readiness to exchange with external devices in the processor status register 43 of the processor 2. D; the control processor sets up the switch 5, for which, via bus 7, an address is entered into register 60 at which control settings codes are read from memory blocks 59, while connection is made

corresponding inputs of the switch to the outputs. The exchange of information between the processor 2 and the external devices is carried out through the exchange node 4, which provides information and control signals. From processor 2, the information from memory block 39 through switch 38 is brought to output register 63 via bus 67, and from bus 68 is output

information tracking signal setting trigger 64 into one state. The absence of a signal on bus 70 indicates that the external device has received information about the readiness to receive new information. The received information is received from the input register 65 via the bus 71 via the switch 38 to the memory unit 39 and is accompanied by a signal via the bus 72.

Reset trigger 66 on the bus 69 indicates that the processor 2 is receiving information and is ready to receive new information. About the end of the exchange

7

shows the reset of the readiness to exchange with external devices in the register 43 of the processor 2. Next, the control processor reconfigures the switch.

If it is necessary to organize interprocessor exchange, the control processor analyzes the readiness of processors 2 for the exchange according to the state of readiness for interprocessor exchange in processor state register 43. Next, the control processor configures the switch 6. After setting up the switch 6, information is exchanged between blocks 39 memory through switches 38 processors 2.

one

Claims (2)

1. A device for centralized control of a computing system, comprising a control process, in order to reduce equipment garbage WHAT, Two switches and a looper are entered into it, the i-th (i 1, ..., n information inputs of the first switch are connected to the iM information inputs / outputs of the device's processors, whose settings are connected to the interprocessor exchange control output of the control processor, the output of the external exchange control of which is connected to the control input of the second switch, the first ith informational inputs-outputs of which are connected to the second informational inputs-outputs of the ix processors of the device, the second information The ion inputs / outputs of the second switch are connected to the i-th information input-outputs ix of the exchange nodes (Device, the output setting of the mode of the control processor is connected to the control output of the loop generator, the output of the confirmation of the completion of the cycle the processor whose output address is connected to the output of the device processor number selection, the input / output data of the control processor is connected to the input / output data of the device processors, the control input of the state of pack 35 40 30 5 2592618 the equal processor is connected to the control input of the state of the processors, the outputs of the processor start bits and the device are formed; 5 cycle bodies are connected to the start outputs of the device, and the control processor contains the command register, the memory of addresses of microinstructions, the address register of memory block - 10 .ti microinstructions, register of microinstructions, clock pulse generator, commutator, memory block, adder, node of general registers, register of result features, decoder micron 5, and the generator output is ct pulses are connected to the synchronization inputs of the micro-command register, the micro-instructions memory block, the micro-commands address register, the 20 micro-commands block and the command register, whose input is connected to the output of the memory block, the output of the command register is connected to the first group of address inputs of the memory block These micro-address addresses are 25, the output of which is connected to the register input of the microinstructions address, which is connected to the second group of address inputs of the microcommand address memory block, the address of the microcoin memory block address and the address input Lok memory block output memory connected to the input microinstructions of microinstruction register, whose output is connected to the input of the decoder which output is connected to switch control input, input of the adder mode code and a control input of the attribute register recording result, the output of which is connected to the third group of addressable, inputs of the memory of microcommand addresses, the output of the attribute of the result of the adder is connected to the input of the result register, the first and second group of inputs-outputs of the adder are connected to the output-input of the node of general registers and the first group of information inputs-outputs of the block memory, the second group of information input-outputs of which is connected to the first group of informatdion input-outputs of the switch, the output of the interprocessor exchange control, the output of the control of external exchange Exit setting mode, the input confirmation of completion of the cycle, output addresses, a data input and an input-output control processor state control processor connected to sootvetst5 0 to the current inputs-outputs of the second group of information inputs-outputs of the switch. 2. A device according to claim 1, characterized in that the cycle former comprises an address counter, a memory block, a group of elements AND, a comparison circuit, a clock counter, an element AND, a clock generator, a start trigger, the output of the counter address being connected to the address input a memory block whose output is connected to the first input of a group of I elements, n outputs of which form the processor startup field and connected to the processor startup output of the loop generator, the stop load of the AND group of the elements is connected to the first input of the AND element, the remaining bits of the group elements form the field of the task cycle and are connected to the first, information input of the comparison circuit, the second information input of which is connected to the output of the clock counter, the reset inputs of the clock counter, the counting input of the address counter and the second input of the AND element are combined and connected to the output of the comparison circuit, the forward output of the trigger trigger is connected to the second input 10 the group of elements And and the start input of the oscillator.contacts, the output of which is connected to the counting input of the clock counter, the output of the element And is connected to the reset input of the trigger trigger, the 15th output of which is connected to the output of confirmation the cycle start of the loop former, the installation of the address counter, the information input of the memory block, and the setup trigger trigger input 20 form the control input of the loop former, 15 WU FIG. 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