SU1257650A1 - Interface for linking exchange processors with peripherals - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in computer systems for exchanging processors with external devices. The aim of the invention is to reduce the hardware cost of the device. The goal is achieved; By the fact that a device that simulates the operation of an external device is inserted into the device containing the external device commutator and two exchange channels, each of which contains an exchange register, a control unit, a module control unit, a program readiness register, a priority unit and a group of subscriber subchannels. and in each exchange channel - a block of elements OR. The unit for simulating the operation of an external device contains a switch for interface signals: the subchannel number register, two ready triggers, two subchannel i-flip-flops, two microprogram nodes - many controls, two AND elements, two OR elements and an exchange register. I Z.P. f-ly 10 Il. 10 ate 01

Description

1257650

The invention relates to digital computing and can be used in computing systems for exchanging processors with external devices (WU) .5

The aim of the invention is to abbreviate. applrau ny1X device costs. ...-,

Fit 1a, 8 shows the block diagram of the device; on phi1.2 - 7, the circuit for switching external devices is rational; in fig. 3 - subscriber subchannel scheme; Fig. 4 is a control block diagram; figure 5 - scheme

M ti with an input of 39 initial settings.

Each of the microprogram control units 11, -1Ij (Fig. 5) contains a micro-command address modifier 40, a micro-command address register 41, a micro-command address decoder 42, a fixed memory unit 43 with an initial installation input 41.

The switch 12 interface signals (6) contains blocks 45 - 4 elements And, blocks 48 and 49 of the elements OR.

U.p. 29 control (Fig. 7) contains

mand, register 5-1 addresses of micro-commands decoder 52 addresses of micro-commands, the node 53 of the permanent memory with the input 54 of the initial installation.

20 Registers 5 - 5 of the program availability is a set of n + 1 flip-flops.

Register 13 of the subchannel number is a set of triggers.

25 In the device, a set of subchannels 3 | - Sn, block 4, register

5 ,, block 6j, register 7 ,, block 8 and block 9, forms the first channel of exchange, the device, and the combination

30 subchannels 3

P 4-1

- zgp

block 4

g

register 5, block 6, register 7, block 82 and block - the second exchange channel. Each of the exchange channels is connected to the corresponding process, a copy exchange (PCO), one of which is in the working (main) mode

subcontrol stations; subroutine- 15, the microhota address modifier 50; yes fig.6 - switchboard of the interface signals; 7 -; the scheme of the nodes of the firmware, control unit simulate the operation of external devices; 4) ig.8a, S, K, 9o, S, 10a, S is a block diagram of the functioning algorithms of units of device level, microprogram unit, control unit of imitation of external device and control unit of subscriber's subchannel, respectively.

The device contains (Fig. 1) kszh mutator 1 external devices, block 2 simulating the operation of an external device, feeds 3 subscribers, priority blocks 4, program readiness registers 5, control blocks 6, exchange registers 7, blocks 8 OR elements, control blocks 9 .

The WIT operation simulation block -2 contains the exchange register 10, nodes 11-11, firmware control, switch 12 interface signals, register 13 of the subchannel number, triggers 14-142 of the readiness of the simulation block trigger 13-152 of the subchannel number, And 16, - 163 and elements OR 17 -17g.

: Switch 1 external devices, (figure 2, V contains blocks 18-27 of the elements And and blocks 22 and 23 elements of the OR.

Each of the subscriber subchannels 3 (FIG. 3) contains the Sub.Cahl exchange register 28, control node 29, service signal register 30, transfer type switch 31, subchannel readiness trigger 32, AND element 33 and OR element 34.

Each of the control blocks 6, - 62 (FIG. 4) contains a micro-command address modifier 35, a micro-command address register 36. The decoder 37 addresses of microinstructions, node 38 permanent pame, and the other - in

much more than a reserve

45

Accordingly, one of the exchange channels is located in a hot reserve,

- and the other, via switch 1, is connected to external devices.

The unit 2 for simulating the work of a VU is designed to carry out a self-check of the computer system that includes this device for interfacing by transferring information from one exchange processor (which is located in hot storage). In another, mainly mode. Information transfer is carried out via a backup channel, exchange unit 2, switch 1 and enters subchannels 3, -3 (3, -3) via standard communication lines.

Blocks 6, - 6, KNOTS 1 b - 11g and

 Ly 29 are used to control, inter alia, the exchange channels, unit 2, the simulation of the work of the VU and the subchannels and have the same principle of operation.

50

M tee with input 39 setup.

Each of the microprogram control units 11, -1Ij (Fig. 5) contains a micro-command address modifier 40, a micro-command address register 41, a micro-command address decoder 42, a fixed memory unit 43 with an initial installation input 41.

The switch 12 interface signals (6) contains blocks 45 - 47 elements And, blocks 48 and 49 elements OR.

U.p. 29 controls (Fig. 7) of the somandrunds, the register of 5-1 addresses of micro-commands, the decoder 52 of the address of micro-commands, the node 53 of the permanent memory with the input 54 of the initial installation.

Registers 5 - 5 of the program availability is a set of n + 1 triggers.

Register 13 of the subchannel number is a set of triggers.

In the device, a set of subchannels 3 | - Sn, block 4, register ....

5 ,, block 6j, register 7 ,, block 8 and block 9, forms the first channel of exchange, the device, and the combination

there is a micro address modifier 50 address 3

P 4-1

- zgp

block 4

g

register 5, block 6, register 7, block 82 and block - the second exchange channel. Each of the exchange channels is connected to the corresponding exchange processor (PCO), one of which is in the working (main) mode

IU, and the other - in

much more than a reserve

Accordingly, one of the exchange channels is located in a hot reserve,

and the other, through switch 1, is connected to external devices.

The unit 2 for simulating the work of a VU is designed to carry out a self-test of the computer system that includes this device for interfacing, by transferring information from one exchange processor (which is in hot standby). In another, the operations are in basic mode. Information transfer is carried out through a backup channel of exchange unit 2, switch 1 and enters subchannels 3, - 3 "(3", - 3) via standard lines of communication.

Blocks 6, - 6, KNOTS 1 b - 11g and nodes 29 serve to control, interchangeably, exchange channels, unit 2 of the IW operation simulation and subchannels 3, and have the same principle of operation.

The next address of the micro-command control is recorded on register 36 (41, 51) of the address of micro-commands, the decoder 37 (42, 52) of the address of micro-commands decodes the address of the micro command 5 and issues a signal to the node 38 (43, 53) of the permanent memory where,; firmware is stored. This signal is read the corresponding micro-co-10 yes. The signals of microoperations that are part of a microcommand come from the output of node 38 (43, 53) of the permanent memory as control signals to various blocks of the device. And by 15, the modifier 35 (40, 50) of the address of microcommands, which performs the analysis external signals and firmware branching.

The device provides exchange20

information of one of the processors of the exchange of the computing system, which includes the device, with a set of external devices, as well as a self-test of this system.25

The device provides a multiplexed mode of information exchange with external devices through an external device switch, and the operation of external devices produces JQ simultaneously and independently from each other.

Mode of information exchange with in-device devices.

The work in this mode is as follows. The exchange processor (not shown), which operates in the main mode, for example, the first one, starts up block 6 and sends the contents of the program readiness register, where the position code records the numbers of external devices from which the processor needs to receive information in register 1 from where then this information goes to registrar 5J of program readiness «| 1. Unit 6 transmits start signals to orders 3, 3. “3”, where they arrive at the element OR 34 and then at the element AND 33. Since the second input of the element And 33 receives signals from the corresponding bits of register 5, then only those nodes 29 are started, which correspond to 1 in register 5, .55

Running these nodes is 29. information is received from the corresponding TDU to the register 28

40

5 10 15

20

25

Q

5 5 0 5

0

and alternately (in accordance with: priority) the issuance of this information in the register 7.

Register 30 is intended for dp latching when receiving from an external device and for issuing service signals to an external device, associated with various exchange steps with a corresponding external device.

The switch 31 is designed for selecting the type of information transfer between the exchange register of the subchannel 28 and the external device (serial or parallel).

Communication with external devices is carried out through switch 1. From block 6 to blocks 18 and 20, a signal is received to allow communication from the slave and information from the slave goes through blocks 26, 22 and 18 to subchannels 3, -3 and from subchannels 3 , - 3 through blocks 20, 23 and 27 - to the external device. Through the blocks 26 and 27 of the signal. passes in the absence of a ban on communication with the control unit from the side of unit 2, i.e., when this unit is turned off.

After receiving the next word on the register 28, the node 29 sets to 1 the trigger 32 and, thus,. Transmits to block 4 a request for an exchange with an exchange processor. After this, the firmware of the subchannel control unit 29 stops.

Block 4j selects the eldest from the number of applicants for the subchannel and, on command from block 6, turns on the node 29 ° of this subchannel. A subchannel thus started transmits its number to the reg 1 1 J register with a position code, which is transmitted to the processor exchange. on the control unit 6, and then from the register 28 subchannel through the block 8-J. El 1ent OR and Register 7 from the subchannel to the exchange processor is transmitted an information word received from the slave.

After this, the cycle of exchanging the word between the subchannels and the volume processor is repeated in the general case already with a word from another subchannel. Thus, there is a multiplexed exchange mode with separation); The time of the communication channel with the exchange processor between many slaves.

When the last word of the array is received in the subchannel, the corresponding attribute is received from WU and the word is passed to the process

 :five

The exchange of the firmware of node 29 of this subchannel stops.

The nogram exchange control is determined by setting and changing the set of external devices (by transferring the contents of the program readiness register) in the process of exchange with external devices.

Computational system self-test mode,

Rabat in this mode is performed against the background of the operation of one of the processors (checked) in the main mode and is carried out as follows ...; .. ...

The second exchange processor operates in the mode of imitation of the work of the slave. At the same time, the exchange processor includes a program for simulating the work of a VU, which forms hard arrays for each external device simulated according to a specific law and according to the initial data specified by the operator. Then this exchange processor switches on block 6, and transmits. On the registrar, the value of the register of readiness of the program, in which I corresponds to block 2 of the simulation of a VU.

Thus, the second processor performs multiplex exchange with only one subchannel, namely, e-block 2.

The contents of register 7 are transferred to register 5, the program readiness and

under the control of block 6 through the elements of the IPI 17 and And 16 to the node 1 i J, receives the signal of the initial start-up KSi. . ., / ..;

When the node turns on, it issues: Through Switch 12, namely through block 49, the signal to prohibit the connection of external devices with the device itself, which enters switch 1 on blocks 26. / 27. -. . ...,

Then the node Mg- issues the block Aj by installing the trigger laj in the I and, since the other subscounts are not included, the call is immediately activated via the block Aj.

The array transmitted from the exchange processor to block 2 has the form:

The word containing the subcount number recorded by the position code (g)

Information word for this subchannel

Subchannel number (j) Information word for the subchannel

The frequency of following information for each subchannel is determined by starting with the actual frequencies of the words from the corresponding external devices.

Thus, first, block 2 receives the word with the number of the subchannel, through which information is then transmitted. This word is transmitted under the control of node 11d. in the register 13 subchannel numbers. 1, recorded in one of the bits of this register, is transmitted to switch I to the corresponding block 24 (for issuing information and service signals to subchannels 3 - 3) and 25 (to receiving service signals from subchannels

3, - h - „) .-. . .

Thus, a link is established between block 2 and one of the sub-channels 3 - 3 of the first exchange channel operating in the basic mode.

Then in register 10 of the second processor; the exchange enters the word ini, pho 5macni, which I is transmitted to the jittered subchannel 3. - 3 ". In this case, the service signals that provide the exchange come from subchannel 3 through blocks 20, 23 and 25 of the switch

1, block 47 of block 12 to the node, and from node II through block 49 and blocks 24,,

22 and 1.8 in subchannel 3 - 3 ". The information from register 10 through block 45 and blocks 24, 22, and 18 and through, switch 31 enters register 28 of subchannel 3 - 3. In this case, the permission to the inputs of blocks 47 and 45 is issued by the node, rij. .

The trigger 15 is used by the node M to distinguish the content of the word transmitted from the second exchange processor — the subchannel number or the information word.

After the transfer of the word through one subchannel 3f - 3 is completed, the contents of register 13 are zeroed and the new value of the subchannel number is entered into it, and the cycle of exchanging the word of information with subchannel 3, -3 is repeated. After the end of the simulation mode from the second exchange processor, the end of exchange feature arrives and node 11 removes the prohibition on communication with the slave in the switch and thus restores the connection of the first exchange processor to the real slave.

Thus, in this mode, for the first exchange processor, the multiplex information exchange with real WUs is simulated without connecting and operating external devices.

in the Imitation mode of operation, the VU can operate any of the exchange processors and, accordingly, any exchange channel.

For nu l a and 3 o b e te n and 25

Claims (2)

1. A device for interfacing exchange processors with external devices, containing a switch for external devices, the first groups of computer inputs and outputs of which are respectively groups of inputs and outputs of communication with external devices of the device and two channels of exchange, each of which contains a register module, control module modulo, program readiness register, priority block and subscriber subchannel group, with each channel exchanging the first information input and the exchange registra and the first course and the control unit form a corresponding output, and control information stvuyuschie yg- Suitable inputs and outputs communication with devices sharing processors, second and third inputs and outputs information exchange register are respectively connected to data inputs; and the outputs of the register of readiness of the program and the modulus control unit, controlled by the input of the exchange control block connected to the second output, the third and fourth outputs of which are connected respectively to the synchronization inputs of the exchange register and the register of readings of the prog frames, and the fifth and sixth approaches f5 20 - t 25 -, 25765.08 responsibly - with the control input of the block, the priority and the synchronization inputs: subscriber subchannels whose ready inputs are connected to the output register of the program readiness register, and the expansion and exit requests, respectively, to the output group and priority input block, the seventh outputs of the first control blocks and the second exchange channels are connected in a typical manner to the first and second address inputs of the external device switch, the second and third groups of informational inputs and outputs of which are connected respectively with the first output slots and the first information inputs of the first and second exchange channel subscriber subchannels, so that, in order to reduce hardware costs, an external device, and in each exchange channel, an OR block; in each exchange channel, the group of information inputs and the fourth information output and input of the exchange register are connected respectively to the second control outputs and the second information outputs the subchannel inputs of the subscriber and the output of the block of elements are connected to the information group. subscriber subchannels, the fifth information output of the exchange register is connected to the second input of the control unit, the first and second information inputs of the imitation unit of the external device are connected respectively to the fourth outputs of the exchange registers of the first and second exchange channels, the first information output - the entrance and the exit of the prohibition are external communications -; . land devices respectively with I information input and output and. f the control input of the fmutator of external devices, the first and second request tsl and the enable inputs of the imitation unit for the operation of external devices are connected respectively to the input groups I: 8 outputs. the priority blocks of the first and second exchange channels, the first and second readiness inputs, respectively, with the output groups of the readiness registers of the first and second exchange channels, the first and second synchronization inputs thirty 35 40 45 50 55 The unit for simulating the operation of external devices is connected respectively to the sixth outputs of the control units of the first and second exchange channels, and the first and second control outputs 5, respectively, to the groups of information inputs of the exchange registers of the first and second exchange channels, 2. The device according to claim 1, which is such that, the unit for imitating the operation of external devices comprises an interface signal switch, the first information output and input of which are respectively an output of prohibiting communication with the external - 15 devices and the third information input of the block, the subchannel number register, two ready triggers, two subchannel number triggers, two microprogram control nodes, two AND elements, two OR elements and the exchange register, the first and informational inputs of the subchannel number and register The first and second inputs of the first and second are, respectively, the first 25 second and second information inputs of the block, the OR elements are cooTBTCTBieHHo, the first and second synchronization inputs and inputs of the block resolution JQ, and the outputs are connected respectively to the first inputs of the first and second elements And, the second inputs of which are the first and the second inputs of the unit are ready, and the outputs are connected respectively to the first inputs of the firmware control nodes, the first outputs of which are connected via the first and second triggers respectively to the first and second outputs of the block requests, and the second outputs and inputs respectively to the inputs and outputs of the first and the second trigger of the subchannel number, the first and second information outputs, the first and second control inputs and the third information output of the subchannel number register are connected respectively to the third inputs and the outputs of the first and second microprocess control nodes and the first information output of the block, the fourth inputs and outputs of the first and second microprogram control nodes are connected respectively to the second and third information outputs and the first and second control inputs of the interface switch of the signals, the second information input of the exchange register connected to the output, the first and second control inputs of which are connected respectively to the fifth outputs of the first and second microprogram control nodes audio, sixth outputs of which are respectively the first and the second control unit outputs yu1tsimi. Kyuschinnin gadgets KPTsO Phie. 1a KPTSOKSucuuHUfi organizer iPus.liS Kit to $ / g M -, // r / f # SS - & | ЛГ7 4% / " , D77CHY7 W /  , KSO AG | KS2 53 P E 50 -jT; "IiMiMaMiijLpM Rt / e.7 FinM .0 Phie.Wah   3 9S Phage. 10a 6 "No Yes Editor M.Nedoluzhenko Compiled by V. Vertlib Tehred L. Serdyukova Order 4958/48 Circulation 671 Subscription VNIISH State Committee of the USSR on inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5  - T g ---- - - - ------ - - .- ----, --- ... Production and Water-Printing Enterprise, Uzhgorod, Projecto st., 4 With j g 106 Corrector S.Cherni