SU1254494A1 - Arbitrator of multiprocessor system - Google Patents

Abstract

The invention relates to computing and can be used to allocate common resources: memory sections and time-division buses between processors in multiprocessor systems. The aim of the invention is to increase the performance of the multiprocessor system upon the receipt of requests for common resources. For this purpose, the multiprocessor system arbiter containing the state memory block and the firmware automator introduced a counter, an address switch, a register, three stack memory units and two groups of stack memory units. 13 il. (Ls

Description

ch1254494

The invention relates to computing and can be used to allocate common resources: memory sections and buses with time division between professors in multi-processor systems.

The purpose of the invention is to increase the performance of the multiprocessor system when receiving requests for shared resources.

FIG. 1 shows the structure of the arbitrator; FIG. 2 is an arbitrator operation firmware graph; in fig. 3 - functional circuitry of the firmware; in fig. 4 - | 5 functional diagram of the attributes decoder; in fig. 5 - the functional diagram of the address switch; Fig. 6 illustrates the construction of the first block of stack memory; Fig. 7 shows a variation of the structure of the second stack memory unit; in fig. 8 shows a variant of constructing a third block of stack memory; in fig. 9 is a variant of building blocks of stack memory of the first group; at 25 of FIG. 10 - a variant of building block-stack memory of the second group; in fig. 11 is a variant of building a block of g am ttl states; in fig. 12 - version of the construction of the counter; in Fig. 13, the Q case construction variant. .

The arbitrator contains (Fig. 1) a microprogram automat 1 (control unit), a first and second blocks 2 and 3 with a current memory, a state memory block 4, tre2

and block 3, one of the outputs of which is connected to the inputs of blocks 9 of the stack memory of the first group. The output of register 8 is connected to the output of the arbiter, whose inputs are connected to the inputs of blocks 2 and 3 of memory.

Block 1 (the firmware automaton is Moore’s control automat, presumed for realizing the arbiter’s firmware (Fig. 2). The automaton 1 (Fig. 3) contains the decoder 11 features, the And 12-39 elements, the elements OR 40-47, the generator of 48 synchronizing pulses triggers 49 - 52. The decoder 11 with characters (Fig. 4) contains the elements AND 53 64 and the elements OR 65-68. Comm1-1 address 7 (Fig. 5) contains the elements AND 69-72, elements OR 7 74, elements AND 75, -83. Block 2 (FIG. Contains a stack memory 84, block 8 of priority analysis, register 86 and elements OR 87-88. Block 3 (f ig.7) contains the stack memory 89, the priority analysis block 9, the register 91 and the OR element 92. The block 5 (Fig. 8) contains the stack memory 93, the register 94 and the OR element 95. Each of the blocks (Fig. 9 ) contains the stack memory 9 register 97 and the element OR 98. Each of the blocks 10 (Fig. 10) contains a memory 99, a register 100 and the element OR 101. The memory block 4 of the states (Fig. 11) contains a memory 102 with random sample, register 103 and

tiy block 5 of stack memory, counter 6, element OR 104. Counter 6 (Fig. 12)

switch ki 9. - 10 and the second group

7 addresses, register 8, block 2, stack memory first

divided into groups

9 -

 W-4

AND

10, 10

g-

Outputs

automaton 1 is connected to the inputs of blocks 2 and 3 of the stack memory, block 4 of the state memory, block 5 of the stack memory, switch 7, register 8 and blocks 9 and 10 of the stack memory of the first and second groups. The inputs of the automaton 1 are connected to the outputs of the blocks 2 and 3, the block 4 of the state memory, the block 5 and the blocks 9 and 10 of the stack memory of the first and second groups. The outputs of the switch 7 are connected to the inputs of memory block 4, blocks 9 of stack memory of the first group, register 8, outputs of block 5 of memory, blocks 9 of stack memory of the first group, inputs of blocks 10 of stack memory of the second group and counter 6. Inputs of the switch 7 are connected to the outputs of the memory block 4, the block 2, the input and output of the block 5, the outputs of the counter 6

2

and block 3, one of the outputs of which is connected to the inputs of blocks 9 of the stack memory of the first group. The output of register 8 is connected to the output of the arbiter, the inputs of which are connected to the inputs of blocks 2 and 3 of memory.

Block 1 (microprogram automaton) is a Moore control automaton, predestined for the implementation of the arbitrator's microprogram (Fig. 2). The automaton 1 (Fig. 3) contains the decoder 11 features, the elements AND 12-39, the elements OR 40-47, the generator 48 clock pulses, triggers 49-52. The decoder 11 features (Fig. 4) contains the elements AND 53-64 and the elements OR 65-68. Kom1-1utator 7 addresses (Fig. 5) contains the elements And 69-72, elements OR 73- 74, elements And 75, -83. Block 2 (FIG. 6 contains the stack memory 84, priority analysis block 85, register 86, and elements OR 87-88. Block 3 (FIG. 7) contains the stack memory 89, priority analysis block 90, register 91, and element OR 92 Block 5 (Fig. 8) contains a stack memory 93, a register 94 and an element OR 95. Each of blocks 9 (Fig. 9) contains a stack memory 96, a register 97 and an element OR 98. Each of blocks 10 (Fig. 10) contains the stack memory 99, the register 100 and the element OR 101. The state memory block 4 (FIG. 11) contains the memory 102 with a random selection, the register 103 and

element OR 104. Counter 6 (Fig. 12)

contains a summing counter 105, a differentiating chain 106 and a diode 107. Register 8 (FIG. 13) contains the register 108, the element OR 109 and the elements And 110, - 11 OR.

Block 2 is used to record and store information about the release of shared resources. Information C; about the release of shared resources by the i-th processor is the addresses of the released J-X memory sections and the m-th bus A | j used by the processor. Block 3 is designed to record and store requests for shared resources. Request 3; processor 1 is the address of the requested memory section A; and the requesting processor. The state memory unit 4 (random access memory unit) is intended for storing the state of the arbitrator. The state of the arbitrator is a collection of tire addresses assigned by the arbitrator to the memory section. The address of the j-th cell of memory 4 is the address of the corresponding memory section.

TSA

The information recorded in the j-th 5th cell of block 4 is the address of the bus assigned by the arbiter of the corresponding memory section. For example, if the address of the zero bus is written in the second cell of block 4, the bus address with the address is zero, the address of the second bus is in the third cell, the address of the first bus is in the seventh cell, then the second memory section ( The address equal to two) 13 appointed the null bus as the arbitrator, the third memory section — the second bus and the seventh memory section — the first bus, and the entire set of addresses is zero.

At once, signs of the presence of requests for a zero memory section, etc. are recorded in the lOg block, and in block 10, signs for the (Z - 1) -th memory section. The arbitrator can work under the condition: only one bus must be assigned on a group of processors requiring access to the same memory section; Only one bus should be assigned to each processor. The order of servicing common resource requests first arrived, first served.

The arbitrator works as follows

In the initial state, it waits for information about the release of shared resources in block 2 or the request for common resources in block 3 (Fig. 1). In this case, the automaton 1 is in the state a. and the HC issues no control and the second bus represents the co-2o signals (Fig. 2). If in artenie arbitrator.

Block 5 is used to store addresses of free buses (unassigned memory sections). Counter 6 is assigned to issue the next occupied address in the event of a request arriving when there is no free bus and the requested section of memory is free. Switch 7 is intended for the communication of arbitrator elements. Register 8 is used to record and output information permitting the requesting processor to use the required shared resources. This information is the address of the requested section.

thirty

35

memory A

CPJ

requesting the bus A process,

designated

40

sora p-t lunnoi of this section of memory.

Stack memory blocks 9 are used to queue processor requests to the desired buses. So, in block 9o, requests of processors queued to the zero bus, etc., are written by the arbitrator, and (and + 3) -th block 9 are requests placed in turn to (and-1) -th bus. Stack memory blocks 10, numbered W + 4 to W + Z + 3 (Yr - lOj.), Are designed to store indications of the presence of requests to the memory sections to which the processors already have access. The sign on the availability of the request to the required memory section is the address of this section. For example, if the request goes to the zero section of the memory, to which a processor already accesses, then the address of this section is written to the unit Yuo. So about

at one time, signs of the presence of requests for a zero memory section, etc., are recorded in block lOg, signs for a (Z - 1) -th memory section are recorded in block 10. An arbitrator can work on the condition that: only one bus must be assigned to a group of processors that require access to the same memory section; Only one bus should be assigned to each processor. The order of serving shared resource requests — first come — first served.

The arbitrator works as follows.

In the initial state, it waits for information about the release of shared resources in block 2 or the request for common resources in block 3 (Fig. 1). In this case, the automaton 1 is in the state a. and the NA gives no control25

thirty

five

0

five

If the bit received a request for total resources, the signal Xj from the output of block 3 (pointer 3) is fed to the automaton 1, which goes to state a, producing a readout signal Y, i.e. request from block 3. After the arbiter completes this microcommand, the automaton 1 enters state a, generating a readout signal Y of information from block 4 of the state memory. To the other input of this block, from the output of block 3, through the switch 7 (if there is a signal Y, j at its input), the address of the requested memory section is supplied. If, as a result of reading to the input of the automaton 1, the signal X is received from the output of block 4, meaning that the requests of the Memory Band have already been addressed by one or several processors, then the automaton 1 goes into state a. In this case, they are given the following signals: Y, - writing the request to one of the 9p blocks - 9vv.,; Y - sign of the presence of the request

behind

in one of the blocks

10 „10

G-1

YC 9

reading information from block 2.

When performing a micro-operation Y, request 3 is fed directly from the output of block 3 to the inputs of blocks 9o

w-

and written to that one

the address of which comes from the output of block 4 through switch 7 (if there is a Y signal at its input) to the inputs of these blocks of the stack memory. When performing a micro-operation Y, the address of the requested memory section, which is already accessed, is supplied from the output of block 3 through switch 7 (with

availability of blocks at its inputs

five

the entrance

signal Y.) on

12

Yus 10

n -1

and is written to the appropriate block.

When implementing a micro-operation Yg, the corresponding control signal is fed to the input of block 2. If the outputs of blocks 4 and 5 (stack pointer 5) do not receive signals X. and X, respectively, to the input of the automaton 1, i.e. if the requested memory section is free and all buses are busy, the automaton 1 switches to the a state, forms the following signals: Y - write the request to one of the blocks 9; Y is an entry in block 4 of the bus address assigned to the requested memory section; reading information from block 2

YS When performing a micro-operation, Yg, request 3 is fed from the output of block 3 to the inputs of blocks 9 and written to the one whose address comes from the output of counter 6 through switch 7 (if there are signals e 1 at its inputs) to other inputs of these blocks.

When implementing a micro operation Yy, the address of the bus assigned by the arbitrator of the requested memory section is fed from the output of counter 6 through switch 7 to the input of block 4 and is written to that cell, whose address comes from the corresponding output of block 3 through switch 7 to the input of block. In this case, the inputs of the switch 7

signals Y, Y are applied; microcommands Y, Y, Yj; my counter 6 is increased by

After fulfilled - contain-

40

nitsu. In the absence of signal X, from the output of block 4 and the arrival of the signal X4 from the output of block 5 to the input of the automaton t, i.e. when the requested memory section is free and there is a free bus, the automaton 1 goes to state a, generating a signal Y.

When the microinstruction Y is executed, the free bus address is intermixed from block 5 and the read address from block 5 input to register 8 and request 3 is written to register 8; incoming block 3 travels through switch 7

45

with you- (at 50

presence at its input signal

Y ")

on

When the microcommand Y is executed, information is read from one of the blocks 9, the address of which determines the empty bus and enters from the second output of block 2 through the switch 7 to the inputs of blocks 9; write to the register 8 of the read information supplied by the input of the register 8 and the address of the free memory section received from the output of block 2

input of register 8. After the arbitrator executes the microcommand Yj, the automaton 1 passes through the switch 7 to the input register to state a, issuing the following 8. Simultaneously with this, the set user Yj is transmitting and reading information from one formation from register 8, resolved from blocks 10, the address of which is the use of the required total resources to the requesting processor;

V

It is the address of the free section of the memory and is output from the output.

recording in the memory unit 4 the status of the bus address assigned to the paged memory section; Yj - reading information from block 2.

When performing a micro-operation, the Y-control signal Yg appears on - the input of register 8, allowing transmission

0

0

;

0

information from it: A (. Af,; and AC on the commutator of shared resources with processors. As a result, the i-th processor will get access to the j-th memory section via the th bus. When performing a micro operation Y, the bus address of the AC assigned to the arbitrator of the requested j-th memory section, is fed from the output of block 5 through switch 7 to the input of block 4 and is written to that cell whose address comes from the output of block 3 () through switch 7 to the input of block 4. When This signals Yg, Y, Yj to the inputs of switch 7. If, as a result of the execution of the microcommand Y, Yj., Yj, or Y, Yj, Yj, or Y ,, Y, Y, respectively, the outputs of blocks 2 and 3 do not receive signals X j and Xg at the input of state machine 1 (which means the absence of information about the release of common resources and requests of processors), then the arbiter finishes the firmware and goes into the initial state (state machine 1 a).

If the output of block 2 signal Xj. is not output, and from the output of block 3, the signal Xj is fed to the input of the automaton 1, then the automaton 1 enters state a, to form the readout signal Y, from block 3.

five

0

ka J. In the case of the arrival of the signal Xc from the output of block 2 on the output of the automaton 1, it goes to the state of control and the signal Y,.

When the microcommand Y is executed, information is read from one of the blocks 9, the address of which determines the empty bus and enters from the second output of block 2 through the switch 7 to the inputs of blocks 9; write to the register 8 of the read information supplied by the input of the register 8 and the address of the free memory section received from the output of block 2

through the switch 7 to the input of the register 8. At the same time, the information from one of the blocks 10, whose address is transmitted, is read

through the switch 7 to the input of the register 8. At the same time, information is read from one of the blocks 10, whose address is

It is the address of the free section of the memory and is output from the output.

block 2 through the switch 7 to the inputs of these blocks.

When the microcommand Y is executed, the input switch 7 is given a signal Y ,. If, as a result of the implementation of this microcommand, the signal X on the availability of the request for the empty bus does not arrive at the input of the automaton 1 from the first output of one of the blocks 9, then the automaton 1 goes to the a, d state and generates the following signals: in block 5; Y - write zero to block 4.

When performing a micro-operation Y, the address of the released bus is entered, which comes directly from the output of block 2 to the input of block 5.

When performing a micro-operation Y, zero is written into that cell of block 4, whose address comes from the output of block 2 through switch 7 (if there is a Yfp signal at its input) to the input of block 4. If after executing the microcommand Y, o, Y to the input of the automaton 1 signal X arrives from the output of block 2, then the automaton 1 passes

to state

at )

generating a signal

reading information Yj from block 2. If the signal is X, 0, then the arbiter performs all actions similar to those in the case when the arbitrator has completed execution of one of the microcommands Y,, Y4, Yj, or Y,, Y,, ff

or y

eight

 7

And on

the entrance of the machine

one

If there is no X3 signal, after the execution of the microcommand Y, the input of the automaton 1 from the output of one of its blocks 9 and one of the blocks 10, respectively, receives signals X- and X on the presence of requests to the empty bus and memory section, the automaton 1 goes into state a , issuing a signal Yj for transmitting Agp information. Hell; , register 8 to the input of the shared resources switch with processors. At arrival at the input of the automaton 1 signal

.and x, 0, then it goes to state a. I will form signals:

YJ re50

giving information from register 8 about the permission to use the requested resources by the requesting processor; Yy write zero in block 4.

55

When the micro-operation Y7 is executed, the zero is written into that cell of block 4, the address of which comes from the output of block 2 through the switch 7

544948

(if at its inputs signals Yg, Yy) to the input of block 4.

After performing the microcommand Y

g

or Yg, Yj, the arbiter performs all the same 5 actions as after the implementation of the microcommand Y (o, Y7. If the automaton 1 is in state a, and the signal X is received, corresponding to the release of common resources from the output of the block 2, the automaton 1 enters state ag, issuing a readout signal Yj from block 2. Next, the operation of the arbitrator is repeated cyclically.

-

 )

15

20

25

thirty

35

50

55

Claims (1)

Invention Formula The multiprocessor system arbitrator containing a state storage unit and a firmware machine, characterized in that, in order to increase performance when receiving requests for common resources, it contains a counter, an address switch, a register, three stack memory units and two groups of stack storage units , wherein the information inputs of the first to seventh address switch are connected respectively to the information output of the state storage unit, the first and second information outputs of the first stack storage unit, the first and second in-. formation outputs of the second stack memory unit, first information output of the third stack memory unit and counter output, inputs of the first through seventh microprogram automat are connected respectively to the output of the pointer of the first stack memory unit, output of the second stack unit memory, output of the memory block sign state, the output of the sign of the third block of stack memory, the output of the sign of the first block of stack memory, the outputs of the sign of blocks of stack memory of the first group and the outputs of the sign of stack blocks second memory: group, the output of the firmware automaton from the first to the tenth are connected respectively with. sync-input of the second stack storage unit and. . the control inputs of the first to ninth address switch; the address inputs of the first and second stack memory units are connected to the address input of the arbiter; the synchronous input of the first stack memory unit is connected to the fifth output of the microprogram automat; inputs, first, second and third sync inputs and register output are connected respectively to the second information output of the third stack memory block, information outputs of the stack storages of the first group, sixth, eighth and ninth outputs of the microprogram automator and the arbiter output, information outputs of the switch addresses one to five are connected respectively to the first and second address inputs of the state storage unit, the counter input, the second information input of the register and the address inputs of the stack stack units ty of the second group, moreover, the second address information output switch connected to the second data output of the third block of stack memory address inputs and a first stack memory blocks ti of the first group, the second address inputs, vho12 etlv / tma hundred uu uu stack 1254494 ten circuits of resolution and synchronization of which are connected respectively with the first information ion output of the second stack memory unit, the third and ninth outputs of the microprogram automat; sync-input and access enable input, state memory unit are connected to the second and seventh outputs of the microprogram automat, the address input, sync input and access enable input of the third stack memory unit are connected respectively to the second information output of the first block the stack memory, the sixth and tenth outputs of the microprogram automat, and the access enable inputs and sync inputs of the stack units of the second group are connected respectively to the fourth and ninth outputs of the microprogram automat. () -u {v () - e} ste i cfne / f Of Cfj At MAZ -. a, i (47 s 2 3  , t - Ha7 ffffSfy Us 56 Q4 57 " five 66 i / s 56 as ,, ff .r V 7 67 Lf4t S five - 6O 7 S five/ 62 6s 6 09 ayu ABOUT // g ./  6.7 from -52 FIG. four .d С y arjcvne / 7f with / тг а CmeiroSaffi / Geamt f7f / 7 / fff J7i From l / w. Fig.b Y5 C / TfSA-ofaur C, yfa3a / r & f7jf with / 7ge z a ajre / per / T / K / oflcf / ffe / T ffc  x FIG. 7