SU1251150A1 - Device for reception of information - Google Patents

Abstract

The invention relates to an information-measuring technique and is intended to determine the deviation of a measured parameter from a predetermined value. The purpose of the invention is to increase speed. The device uses hardware linearization of the characteristics of the sensors through the use of an address decoder and a memory block that contains the mathematical model of the sensor. The operation of the device is based on the determination of the digital value of the signal from the sensor output and the formation by means of counters of the address at which the corresponding value of the measured value is recorded in the memory unit. 1 zi f-ly, 2 ill. 1C pr

Description

The invention relates to a measuring and measuring technique and is intended to determine the deviation of a measured parameter from a predetermined value.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a functional diagram of the device; in fig. 2 - time diagram of the device.

The device for receiving information contains a sensor 1, the first 2 and second 3 signal level converters, the first decoder 4, the setting unit 5 of the installation, the analog-digital converter 6 containing the first and second counters 7 and 8, the first 9 and second 10 pulse shapers, block 11 memory, trigger 12, the first and second registers 13 and 14, the second decoder 15 and the indicator 16.

The decoder 4 is required to provide (at any setpoint value) a sample of that cell of block 11, in which the binary-decimal course of deviation of the measured value Li from the set value of the setpoint Aust is stored:

LA A - Ay. "

In fact, by means of the decoder 4, the device characteristics are mixed, by changing the address code generated by the counter 8. The decoder 4 can be implemented on a permanent memory, K573PF2 ROM (2 pcs.) Or programmable logic matrices (PLM ) K556 PT2 (2 pcs.)

The number L and the size of the sub-signal of the decoder 4 must be equal, respectively:

t Schach Ampmp. 17

L, PPR lOgiL

The device (Fig. 1) can operate in two modes: measurement (set by signal and from the second output of setpoint 5) and setting (indication) of the setpoint (set by giving signal U from the first output of setting 5).

The operation of the device in the measurement mode is illustrated by the diagram in FIG. 2. On the signal I4, the counter 7 provides for the formation of the interval Ui at the output, on the leading edge of which the NO code is output from the output of the decipheror 4 to the counter 8. During the interval Ui, the counter 8 counts the number NJ: frequency periods

N, f.-t ,, (1)

where ti is the duration of the signal Uj.

The code on the outputs of counter 8 by the end of the interval ti. has the meaning:

Na Ni + Ng-2, (2)

where n is the number of binary bits of the counter 8

The signal Uj from the cell block 11 with address no. reads the binary-decimal digital code of the measured value and

signal and entered into register 14. At the same time, the signal 7 restarts from the signal 7. Since the signal Ug O, the outputs of register 13 are disconnected from the input of the decoder 15, the indicator 16 continuously illuminates the value of the measured value, the binary-decimal code of which is read from the outputs register 14 and is converted into an indicator code by a decoder 15. A single measurement cycle has the following form:

t4 tt + ti + tj,

where ti is the interval duration

accounts;

(i-5) -io c is the duration of the U signal;

tj (o -3} -w i-time retrieval of information

from block 11 and initial

counter settings 7; K -target counter 7.

In the setting mode (indication) of the setpoint, a binary-decimal setpoint code is output from the output of setpoint 5 to counter 7 with a Ug signal and an indication of this code in the indicator 16 due to the presence of a high level Uj at the input of the register 13. At the same time, the operation of the rest of the circuit elements of FIG. 1 does not change, however, the outputs of register 14 are disconnected from the input of the second decoder 15 by signals 17.

In the proposed device, a hardware implementation of the sensor characteristic is used by using the decoder 4 and the memory block 11 implemented as a reprogrammable read-only memory. Due to the rejection of the software processing of the sensor signals, the speed of the device is improved, which makes it possible to use it to control fast-changing parameters.

Claims (2)

1. A device for receiving information containing a sensor, an analog-to-digital converter, a setpoint adjuster, a memory unit, registers and an indicator, characterized in that, in order to improve the speed of the device, decoders, level transmitters of signals and a trigger are inserted into it, the first and The second sensor outputs, respectively, through the first and second signal level converters are connected respectively to the first and second inputs of the analog-to-digital converter, the first and second outputs of which are connected respectively to the first the second inputs of the memory block, the first, second and third SETOUTS of the setpoint adjuster are connected respectively to the first trigger input, the combined second trigger input and the third analog-digital converter inputs and the combined inputs of the first decoder, the fourth analog-digital converter inputs and the first inputs of the first register, the outputs of the first decoder are connected to the fifth inputs of the analog-to-digital converter; the first and second outputs of the memory unit are connected to the first inputs of the second; About the register and the combined second input of the second register and the sixth input of the analog-digital converter, the first and second outputs of the trigger are connected respectively to the third input of the second register and the second input of the first register, the outputs of the first and second registers are combined and through the second decoder to the inputs of the indicator . 2. The device according to claim 1, characterized in that the analog-to-digital converter contains counters and pulse shapers, the output of the first counter is connected to the inputs of the first and second pulse shapers, the output of the first pulse shaper is connected to the first input of the second counter, the second and third inputs of the second the counters and the first, second, third and fourth inputs of the first counter are respectively the first, fifth, second, third, fourth and sixth inputs of the analog-to-digital converter, the outputs of the second counter and the output of the second The pulse former is respectively the first and second outputs of the device. FIG. 2