SU1249507A1 - Multiplying device - Google Patents

Abstract

The invention relates to computing and can be used in optoelectronic computing devices that perform operations on fixed-point decimal numbers. The aim of the invention is to expand the scope of application by providing the possibility of processing information with a natural comma position. This is achieved in that the multiplier contains a comma-value adder. Using a position analysis node in the proposed device allows the multiplication of decimal numbers with the natural position of a comma with high speed, provided by the device for multiplying decimal numbers, taken as a prototype. At the same time, the multiplier can efficiently perform processing of integers, which in this case can be considered as a special case of representing decimal numbers; with the natural position comma,,; i, the fractional fraction of the numbers is equal to the bullet. 3 silt, 1 tab. Go 4; o ate

Description

The invention relates to computing and can be used in optoelectronic computing devices that perform operations on decimal numbers with the natural position of the comma.

The aim of the invention is the expansion of the field of application due to the possibility of processing information with a natural comma position.

FIG. 1 is a block diagram of a multiplier device; in fig. 2 is a schematic diagram of the adder of the position analysis of a comma; in fig. 3 - the algorithm of the software control unit.

The multiplication device (Fig. D) contains a multiplier register 1, adder 2, a multiplier of 3 multipliers, adder 4 of the position analysis of a comma, a counter 5 of the multiplier of the multiplier, software control unit 6 and node 7 of the character analysis. The control inputs 8 and 9 of the multiplier register are connected to the outputs of the software block 6 of the control; 1 and are respectively the inputs of the control of the multiplier, which is controlled by the information input 10 of the register i, and the left shift of the register contents 1 m. The high (fe + l) -ro output of the adder 2 is connected to the low-order information input of register 1, and the control input 11 of register 1 of the multiplier and the control input 12 of the sign bit of the register are connected to the outputs of software block 6 of control and are correspondingly, the input of the zeroing register 1 and the input of the control of the output of the product sign into the sign bit of register 1. The information input of the sign bit of register 1 is connected to the output of the sign analysis node 7, one of the inputs of which is connected to the output of the sign bit register 1 and to the second input comes a multiplicative sign. The control input 13 of the senior k-ro bit; 1, and the register 1 is connected to the corresponding output of the program control unit 6. The information multi-bit output of the higher fe-i O bit of register 1 of the multiplier is connected to information input 14 of the generator 3 times multiplicand, and the output 15 of the sign zero in the –th bit of register 1 is connected to the corresponding, - P1IM input of the program control unit 6.

The control input 16 of the adder 2 is connected to the output of the program block 6 of the controller and is the control input of information recording in the adder 2, and the information input 17 of the adder 2 is connected to the information output of the generator 3 times multiplicative.

The control inputs 18 and 19 of the adder 2 are connected to the outputs of the program block 6 of the control and are respectively the zero input and the input of the left shift information in the adder 2. Bxozi

0

0

0

0

five

20, the start of the software control unit 6 is the device start input.

The control input 21 of the generator 3 times multiplicands is connected to the corresponding output of the software control unit 6 and is the control input of the multiplier recording. The information input 22 of the 3 times multiplier generator is the input of the A multiplier A. The control inputs 23-25 are connected to the outputs of the software control unit 6 and are the control input of the read control of the corresponding multiple multiplier to the adder 2, the installation input to the initial state of the generator 3 multiples of the multiplier and the input of the formation of multiples of the multiplicand in the generator 3, respectively.

The control inputs 26 and 27 of the position analysis adder 4 are connected to the corresponding outputs of the software control unit 6 and are the zero input and the write control input, respectively.

The information inputs 28 and 29 of the comma-position adder 4 are the inputs for recording the fractional part of the multiplicand and potential, respectively, and the outputs are connected to outputs 30 and 31 of the position indication of the com- puter device, respectively.

The control input 32 of the counter 5, which is connected to the output of the software block 6, is the control input of the data multiplier on the information input 33 of the counter 5. The control inputs 34 and 35 of the counter 5 are connected to the corresponding outputs of the program. control unit 6 and ch.ch are respectively the zero input and the subtract input of the counter 5. The output of the zero zero Po of the counter 5 is connected to the corresponding input of the programm control unit 6. From the outputs of pei-ister 1 and adder 2, the values of I- and Pa are removed, respectively, of the higher and lower order bits.

The totalizer analysis aggregate 4 (Fig. 2) consists of its own optoelectron (2fe-il) -ro discharge module 36, an additional regenerative optocoupler 37 and an optoelectron key 38. Each of the () -x bits of the optoelectronic module 36 represents It is a regenerative optocoupler 39 consisting of a source of light 40, a first 41, a second 42 and a third 43 photo receivers, the combined outputs of which 1 are switches to the base of transistor 44. The first ({) terminal 41 of each regenerative ontron 39 is optically connected to source 40 light of the same regenerative op throne 39, the second photodetector 42 of all regenerative optocouplers 39, except the first, is optically connected to the source 40 of the previous light, the second photodetector 42 of the first regenerative optocoupler 39 is optically connected to the information inputs 28 and 29

The position analyzer 4 of the commanding unit, which are the recording inputs of the fractional fraction of the multiplier PB and the multiplicand RA, respectively, the third photodetector 43 is optically connected to the source 40 of the next discharge light. The base of the transistor 44 in each bit is connected via the first photodetector 41 to the bus 45 of the positive pole of the power source, through the second photodetector 42 to the electrical control bus 27, and through the third photo receiver 43 to the output of the optoelectronic switch 38.

In addition, the base of the transistor 44 is connected to the anode of the diode 55, the cathode of which is connected to the zeroing terminal 26. Collector

Register 1 is its elder digit. At the same time, the value 5 of the multiplier M in the presence of a signal at its control input 32 is recorded in the counter 5 by the information input 33. In the analyzer 4, the analysis of the position of the recording result on the information input 28 is recorded in the fractional value PB of the fractional part of the multiplier. It then records the second operand A in parallel with the discharge into the generator 3 multiples of the multiplier, arriving at its information input 22. The adder 4 of the analysis for information input 29 records the RA bit value of the fractional part of the multiplicator A. Simultaneously with the recording of the second operand A, the transistor multiplier 44 through the source 40 of the light of the 5 bodies B and the multiplicand A are fed to the inputs

It is connected to bus 45, and the emitter is connected to the common bus. The optical outputs of the light sources 40 of the first (L + 1) regenerative optocouplers 39 are the outputs 31 of the totalizer 4 of the analysis, and the optical outputs of the regenerative optocouplers 30, starting with (st + 2) -th and up (2 / fe- - l) -ro, are outputs 30 of adder 4.

The additional regenerative optron 37 consists of the first 46 and second 47

The character analysis node 7, which forms the product mark, enters the sign bit of register 1 of the multiplier in the presence of an enable signal at its control input 12. Multiplicated multiplicators are generated in generator 3 in the presence of signals from the control input program 6 25 generator 3 multiplicands. Multiplication occurs, starting with the eldest bits of the photodetectors, resistor 48, the first multiplier. In case the factor B

the common pins of which are connected to the base of the transistor 49, and the source 50 of light, the first pin of which is connected to the collector of the transistor 49. The second pin of the resistor 48 is connected to the electrical control is an incorrect fraction, i.e. when after the multiplier and before the high significant digit of the multiplier if there is a certain number of zeros, then the fraction is normalized by successive left shift

the main bus 27. The emitter of the transistor 49 30 information in the register 1 for one decimal

and the second terminal of the second photodetector 47 is connected to a common bus, the light source 50 is optically connected to the first photoreceiver 46, the second photoreceiver 47, and also the photoreceiver 51 of the optoelectronic switch 38. The second terminals of the source 50 of the light 35 and the first photoreceiver 46 are connected to the bus 45. Optoelectronic switch 38 consists of a photodetector 51, a mode resistor 52, the first combined terminals of which are connected to the base of the transistor 53, and the load resistor 54.

The collector of the transistor 53 through the load resistor 54 is connected to the bus 45, which is also connected to the second terminal of the mode resistor 52. The emitter of the transistor 53 and the second terminal of the photoreceiver 51 are connected to the common bus.

The device for multiplying decimal numbers works as follows.

The installation of the multiplier 1, adder 2, generator 3 multiples of multiplicand, adder 4 analyzing the position of the comma and counter 5 by signals received at the control inputs II, 18, 24, 26 and 34 of these blocks, respectively, takes place.

The first operand В is recorded in register 1 by information input 10 in the presence of a record control signal at input 8 of register 1. And the multiplication B is recorded so that in the first bit

discharge and simultaneously reducing the contents of counter 5 by one. The shift continues until in the higher ft-M resolution of the register 1 it is not the highest significant factor of the multiplier, as evidenced by the appearance of its signal at its output 15.

From the information multi-bit output of the higher / gth digit of the register 1. Multiplier to the input 14 of the generator 3, Q receives an information signal that selects a multiple corresponding to the value of the decimal digit in the ith bit of the register 1.

The corresponding multiple of the multiplicand enters the information input 17 of the adder 2 in the presence of a control signal 45 by reading at the control input 23 of the generator 3 multiples of the multiplicand. The selected multiple is summed with the content of adder 2 in the presence of a recording control signal at the control input 16 of the adder 2. The value of the multiplier 5 counter decreases by one and y after the signal arrives at its control input 35. Then, the left shift is one decimal bit of information in register 1 of the multiplier and adder 2 under the action of the shift control signals supplied to the control inputs 9 and 19 of the multiplier register and adder 2, respectively. At the same time, the information from the senior (k-i-D-ro bit of the adder 2 shifts50

55

Register 1 is its elder digit. At the same time, the value 5 of the multiplier M in the presence of a signal at its control input 32 is recorded in the counter 5 by the information input 33. In the analyzer 4, the analysis of the position of the recording result on the information input 28 is recorded in the fractional value PB of the fractional part of the multiplier. Then it writes down from the second operand A in parallel to the discharge into the generator 3 multiples of the multiplier, arriving at its information input 22. The adder 4 of the analysis on the information input 29 records the RA bit value of the fractional part of the multiplicator A. Simultaneously with the recording of the second operand A the multiples tel B and the multiplicand A arrive at the inputs

The character analysis node 7, which forms the product mark, enters the sign bit of register 1 of the multiplier in the presence of an enable signal at its control input 12. Multiplicated multiplicators are generated in generator 3 in the presence of signals from the control input program 6 25 generator 3 multiplicands. Multiplication occurs, starting with the most significant bit, is an irregular fraction, i.e. when after the comma and before the leading significant digit of the multiplier there is a certain number of zeros, the fraction is normalized by successively shifting to the left

five

discharge and simultaneously reducing the contents of counter 5 by one. The shift continues until in the higher ft-M resolution of the register 1 it is not the highest significant factor of the multiplier, as evidenced by the appearance of its signal at its output 15.

From the information multi-bit output of the higher / gth bit of register 1. The multiplier to the input 14 of the generator 3 receives an information signal that selects a multiple that corresponds to the value of the decimal digit in the ith bit of the register 1.

The corresponding multiple of the multiplicand enters the information input 17 of the adder 2 in the presence of a control signal 5 by reading at the control input 23 of the generator 3 multiples of the multiplicand. The selected multiple is summed with the content of adder 2 in the presence of a recording control signal at the control input 16 of the adder 2. The value of the multiplier 5 counter decreases by one and y after the signal arrives at its control input 35. Then, the left shift is one decimal bit of information in register 1 of the multiplier and adder 2 under the action of the shift control signals supplied to the control inputs 9 and 19 of the multiplier register and adder 2, respectively. In this case, the information from the senior (k-i-D-ro bit of the adder 2 shifts

five

. It is in the low-order bit of register 1 of the multiplier at the input {input terminal, the value of the k-ro high-register 1 is lost, and the low-order bit of adder 2 takes a zero value. In the case of the presence of a significant zero in kM of the old bit of the dereg 1 register multiplier, i.e. the signal of the sign of the zero signal at its output 15, only a left-decimal shift of information occurs in the register 1 of the multiplier and in the adder 2 in this way and reducing the value of the counter 5 by one. If counter 5 assumes a zero value, as evidenced by the appearance of a single signal P (: at the corresponding input of the control unit 6, the multiplication operation is completed and the CTapniero-th register register 1 is multiplied by the reset signal; The input input 13 of this bit. The sign and the highest bits of the product are in register 1, and (/ r - (- 1) -e minor bits are stored in adder 2.

The adder 4 of the position analysis of the comma (Fig. 2) works as follows.

; 1, l of the readiness of the on-electronic module 36 for recording information on bus 45, the voltage of the power supply voltage is applied. The signal arriving via bus 26 zeros all regenerative ontropes 39. If there is a Yongfig Yangha pulse of a positive field capacity on the electrical bus 27 and an optical signal on the input 28 of the fractional part of the first operand B of the output, it goes into the excited the state of the first regenerative optocoupler 39 and the additional regeneration of the operative array 37. The optoelectron key 38 is triggered, the electrical output of which removes the awful level of the negative signal.

Then, depending on the length of time the optical signal is tuned to the input 28, the second, third, etc., regenerative optocouplers 39 sequentially operate, while the resetting of the nerve, second, etc., regenerative ontropes 39 does not occur. () go ;, um, since recording information to the module 36 from the electrical output of the electronic key 38 is removed a low level of negative potential.

After completing the recording of information into the module 36 dono: a powerful regenerative optocoupler 37 is nullified, the onto-electronic switch 38 is not switched off, and a high level of negative notation is removed from its electrical output; 1a, and the p4M of regenerative optocouplers 39 module 36 is removed, except for This is the only one in which you remain understudy: the ipformatics unit, due to the optical feedback from the ontic output J-ro of the regenerative optocoupler 39 to the input (r1} -th regenerative ontron 39.

Thus, in the adder 4, the analysis of the zero; e; and then write down the 1c value

of the fractional part of the operand in the form of a unitary code 0 ... 010 ... 0, where the unit is in the corresponding bit of the optoelectronic module 36. Similarly, the value in the adder 4 is analyzed

of the fractional part of the second operand, with the only difference being that the optocouplers start to operate from the last one, which was triggered when recording the previous information in accordance with the duration of the optical

signal on the bus 29.

Thus, in the adder 4 of the analysis of the position of a comma, the sum of the magnitudes of the fractional parts of the multiplier RA and the multiplier RV occurs.

The result is presented in the form of a unitary

code 0 ... 010 ... 0. Considering the fact that each bit of the optoelectronic module 36 of the adder 4 of the analysis, starting with the first and up to (2 / g + 1) -th, corresponds to the decimal bit of the adder 2 and register 1, starting

from the nerve bit of adder 2 and to the k-ro bit of register 1, the presence of a unit in a certain bit of modulo 36 corresponds to the position of a comma before the digit in the corresponding bit of adder 2 or register 1.

Program block 6 corrupts the execution of the algorithm for multiplying decimal numbers in a natural comma position.

The control and logic signals necessary for controlling the operation of the device are listed in the table.

The sequence of the formation of the control of the Y - / i signals is shown in the graphic diagram (Fig. 3).

15 X i Signal signal zero in the kth discharge of register 1 (when recording is enabled in the adder 2, reading 3 times from the generator and decreasing per unit of information in counter 5)

 Xj Signal signal zero of counter 5 (with X2, 1 permission to zero the bit of register 1)

X „Mode (with X, performing a multiply operation)

III

Continuation of table 3

Y; 17 Resetting the k-th bit of register 1

15

20

25

state of the generator 3 times multiplicand

 Installation in the initial

state of adder for position analysis comma

Yj, Record in register 1 V7 Record in counter 5

KM Record in adder 4 analysis of position

Record in the generator 3 multiple multiplicands

UY Entry to character register bit 1

UL Formation of Multiple

multiplier in generator 3

 Shift left in register 1 35

, Subtraction units in the counter 5

U, Record in adder 2

Y15 Reading from the generator multiples of the multiplicand

thirty

 ABOUT

Y16 Shift left in the adder 2 5

1. The multiplier register 1, the adder 2, the adder 4 of the position analysis, the generator of 3 multiples of the multiplicand and the counter 5 are set to the initial state.

2.In register 1, the multiplier records the value of the first operand; in adder 4, the position analysis of the comma is the value of the fractional part of the first operand.

yes, counter 5 is the bit size of the first operand.

3. In the 3 times multiplicand generator, the value of the second operand is recorded. in adder 4, the analysis of the position of the comma of the bit size of the fractional part of the second operand; in the sign bit of the register I, the sign of the result.

4. Multiples of a multiplicand in a generator of 3 multiples of a multiplicator are formed.

5. Determines the equality of the decimal digit in the highest kth de register 1 of the multiplier to zero. If the decimal digit in the senior kth digit of register 1 of the multiplier is zero, then a left decimal shift of information in register 1 and a decrease in the contents of counter 5 by one. The shift occurs until the significant digit of the multiplier appears in the senior / zth deregister 1 register.

6.If the tenth digit in the start-up k-M register of the register 1 multiplier does not equal to zero, then the corresponding multiple is sampled from the generator 3 times, the contents of the adder 2 are combined with the selected multiples, and the counter 5 is reduced by one.

7. It is determined that the value of the counter 5 is zero. If the value of the counter 5 is not equal to zero, then there is a shift to the left by one decimal bit of information in the adder 2 and the register 1 of the multiplier.

8. The equality is well defined; by: 1, the decimal digit in the highest fe (m times) - de register 1 multiplier. 1If the decimal digit in the highest kth deregister of register I is zero, then the value of counter 5 decreases by one, and then step 7 is executed.

9.If the value of the decimal digit r, the most significant sth of the dereg register 1 is not zero, step 6 is satisfied.

10. If the value of the counter 5 is ny; iK), then the ciapniero k-ro p: p of register 1 is wrapped up. The operation has been completed.

Claims (1)

Invention Formula A device for multiplication containing a multiplier register, a summation torus, a multiplicative multiplier generator, USC character generation, a counter and a software control unit, the multiplier input connected to the multiplier register information input, the multiplier information input connected to the multiplier information input multiplicand, the output of the sign bit of the register multiply is connected to the first input of the node of the format of the first signs, the outputs of the program control loop from the first to the third are connected respectively to the input I give zeroing register multiplier, accumulating adder and counter, fourth and binary outputs of the software control unit are connected to the control inputs of the register register multiplier and accumulating adders, the output of the higher information bit of the accumulating adder is connected to the information input of the younger information bit of the multiplier register, the sixth output of the software control unit is connected to the control input of the counter, the output of the sign of equality to zero of which is connected to the input of the sign of the end of the program block count control, the seventh, eighth and ninth outputs of which are connected respectively to the shift control input of the multiplier register, the counting input of the counter, the shift control input of the accumulating adder, the twelfth output of the software control unit is connected to the control input of the multiples of the multiparable, the start input of the software control unit is connected to the device start input, the information input of the counter is the input of the device multiplier, the tenth and eleventh outputs of the software control unit connected to the control inputs of recording the sign and zeroing the highest k-ro bit of the multiplier register, respectively, the output of the zero sign of the most senior k-ro bit of the multiplier register is connected to the input of the sign of performing the addition in this cycle of the software control unit, the second input of the sign forming unit is connected to the input sign of the multiplicable device, the output of the senior k-ro 0 five 0 the register bit multiplier is connected to the control input of the multiplicity multiplier of the multiplier factor, the output of which is connected to the information input of the accumulating adder, the discharge outputs of which are connected to the outputs of the low-end HJHX output of the device, the outputs of the register bits of the multiplier are connected to the outputs of the higher-order output devices, the twelfth, thirteenth, fourteenth and fifteenth outputs of the software control unit are connected to the setup input to the initial state, the recording control input with the read control input and the control input of the formation of multiple generators multiples of the multiplicand, respectively, characterized in that, with, the aim of reducing the field of application by providing the ability to process information from the natural comma position, the device contains a comma position analysis adder, two information inputs of the position analysis adder are connected to the bit inputs of the fractional parts of the multiplicand and the device multiplier, respectively, and the outputs of the adder's position analysis adder The sixteenth and seventeenth outputs of the software control unit are connected to the input of the installation to the initial state and the control input of the record of the adder of the position analysis of the commanding unit, the output of the sign generation unit is connected to the input of the sign bit of the multiplier register. R, RV t ro 27 FIG. one