SU1246400A1 - Demodulator of signals keyed by minimum frequency shift with error correction - Google Patents

Abstract

The invention relates to telecommunications and can be used in receiving devices. The purpose of the invention is. ki - the increase in noise immunity. The demodulator contains a phase shifter G, delay elements (EZ) 2,5,8,19,21, phase detectors 3,9, signal conditioners 4,10, elements DRIPPING OR 6,7,11,18,20, analysis blocks opm- , side (UAS) 12,16,17, elements OR 22, 23. BAO are made of an EXCLUSIVE OR element 13, delay element 14 and a decoder 15. With the help of the phasor, the spatula 1. eliminates the phase multiple of 90. EZ 2 , included in the information channel, carries out a delay of one clock interval, and EZ 8, included in the test channel, - by two clock intervals. EZ 2.8 and phase detectors 3.9 use the simplest autocorrelation demodulators in the corresponding channels. At the output of the EXCLUSIVE OR 6 element, a check sequence is formed. Element EXCAVATING OR 7 compares two AHs. As a result, errors occur. Errors are analyzed in the BAO and corrected by the elements EXCLUSIVE ШШ 18,20, 11. 2 Il. (L atoi Output a and

Description

I12

The invention relates to telecommunications and can be used in radio receivers for receiving signals manipulated by a minimum shift.

The purpose of the invention is to increase the noise resistance,

Figure 1 shows the structural electrical circuit of the demodulator of signals manipulated by a minimum frequency shift with error correction; Fig. 2 shows a comparative noise immunity diagram of a proposed and a known device depending on the probability of errors in the communication link.

The demodulator of the signals manipulated by the minimum frequency shift contains the phase shifter 1, the first delay element 2, the first phase detector 3, the first driver 4 signals, the second delay element 5, the first 6 and the second 7 elements, SPARED (t CHAPTER 3, the third delay element 8, the second phase detector 9, the second signal generator 10, the output element EXCLUSIVE OR 11 and the first error analysis block 12, consisting of the element EXCLUSIVE OR - 13, the delay element 14 and the decoder 15, and also contains the second 16 and third 17 blocks of error analysis , rety an EXCLUSIVE-Iggi 18

the fourth delay element 19, the fourth element EXCLUSIVE OR 20., the fifth delay element 21 and the first 22 and second 23 elements OR.

The demodulator of signals manipulated by the minimum frequency shift with error correction works in the following manner.

The input radio signal from the output of the matched filter (not shown) is fed to the phase shifter 1 through 90 ° of the information channel, which serves to eliminate the phase uncertainty of a multiple of 90, and then through the first delay element 2 for the period of one clock interval - to the first input of the first phase detector 3. At the same time, the input radio signal is also fed to the input of the test channel - to the input of the third delay element 8 at a time equal to the duration of two clock intervals, and then to the input of the second phase detector 9 Elements 2 and 8 back The holders and phase detectors 3 and 9, respectively, of the information and test channels, are the simplest autocorrelation demodulators. The signal at the output of the first phase detector 3 in the information channel is determined by the phase shift 9 between the previous and current dressing.

. -but

S 1 T T;

oL, V, ft-f.

Similarly, in the test channel, the signal at the output of the second phase detector 9 is determined from the expression

U,

U

cos

.cf ... .0.7G}.

signals

The first channel information shaper 4 and the second test channel shaper 10 make decisions about the values of received messages in accordance with the rule

V

1 for p L O O at U 0.

15

thirty

On the OUTPUTS of the first element of the ICTCHUME OR 6, a test sequence V is formed,

by adding modulo two sequences V from the output of the first driver 4 signals and its delayed second element.m 5 delay

for the period of the clock interval of the copy. The second element, EXCLUSIVE OR 7, compares the check sequences V, and V. Moreover, as a result of the comparison,

the following situations: there are no errors in both of the V and Vj sequences; are present in one of the sequences V or V j errors-. ki are present in the.

telienet x

I - -When there is no output error

The second element, EXCLUSIVE OR 7, forms a combination of zero parcels. This combination arrives at

blocks 12 ,, 16 and 17 error analysis.

In this case, the decoders 15 of these blocks do not work, with the result that the signal from the logical c, the outputs of the blocks 1.16 and 17 of the error analysis is fed to the corresponding inputs of the third, fourth and output elements of the EXCEL SCHEEE OR 18, 20 and 11, and the information signal c second output

3

element 5 delay passes to the output of the device without correction.

In the event of errors in the information or test channel, the output of the second element is EXCLUSIVE

.OR 7 appears one of the combinations; 0011.- with a single error; 0101 - with a double error; 1001 - with a build error.

Decryption of errors of a certain type is carried out in one of the blocks 16,17 and 12 error analysis.

In case of a single error, the correction signal (logical 1 signal) from the output of the first error analysis block 12 through the second element OR 23 is fed to the first input of the output element SPARED OR 11, causing an inversion of the corresponding symbol in the information flow. When the error is doubled, the correction signal from the first 12 and third 17 error analysis blocks is received through the first 22 and second 23 elements OR

.to the inputs of the fourth 20 and output 11 elements EXCLUSIVE OR, causing the inversion of the corresponding two adjacent characters in the information flow. With a built-in error, the correction signal from the second block 16. error analysis

influences. on three elements EXCLUSIVE | | PIACHTSEE OR 18,20 and 11, there is a inversion of three consecutive characters in the information flow.

When symbols simultaneously fail in informational and test channels, undetected errors occur, but the probability of their occurrence is lower than in a known device, due to the detection of not only single errors, but also errors of greater multiplicity. If it is necessary to detect error packets of a multiplicity of more than three, additional error analysis blocks, OR elements and chains of series-connected EXCLUSIVE OR elements and delays, included according to the principle of the circuit in FIG.

Claims (1)

Invention Formula A demodulator of signals manipulated by a minimum frequency shift with error correction, containing series-connected phase shifter, the first delay element, the phase detector and the signal conditioner, the second delay element and the first and second elements EXCLUSIVE OR, pos400 successively connected third, delay element and second phase detector and signal conditioner, output element EXCLUSIVE OR, the output of which is the output of the demodulator, and the first error analysis block consisting of series-connected element EXCLUSIVE OR, delay element and decoder, the second input and the output of which is connected to the inputs of the EXCLUSIVE OR element and is the input and output of the error analysis block, the inputs of the phase shifter and the third delay element and the second inputs of the first and second phase details The two sectors are combined and are the input of the demodulator; the outputs of the first and second signal conditioners are connected to the second inputs of the first and second, respectively. EXCLUSIVE OR elements, characterized in that, in order to increase noise immunity, the second and third error analysis blocks are introduced in series, the third EXCLUSIVE OR element, the fourth delay element, the fourth EXCLUSIVE OR element, and the fifth fifth element, the first and second elements are connected in series elements of RSHI, whose inputs are connected to the outputs of the error analysis blocks, and the output is connected to the first input of the output element EXCLUSIVE OR, the second input of which is connected to the output of the fifth delay element, while the output of the second The delay element is connected to the first input of the third element EXCLUSIVE OR, the output of the second error analysis block is connected to one input of the first OR element and to the second input of the third element EXCLUSIVE OR, another input and output of the first OR element are respectively connected to the output of the third error analysis block and. to the second input of the fourth element EXCLUSIVE OR, and the third and fourth inputs of the decoder and the output of the delay element of each block. The error analysis and its corresponding first and second additional inputs and additional output, with the additional output of the first error analysis block connected to the first additional inputs of the second and third error analysis blocks, the additional output of the second error analysis block is connected to the input of the third error analysis block and to the first additional to the input of the first error analysis block, additional output of the third block, error analysis connected to the input of the first error analysis block and to the second additional input of the second block error analysis, the output of the second element of the IS1A1 is STARTING OR connected to the input of the second error analysis unit and with the second additional inputs of the first and third error analysis. 2 Editor 0. Head Compiled by V. Zenkin Tehred L.Oleynik Proofreader E.Sirohman Order 4024/57 Circulation 624 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 . Production and printing company, Uzhgorod, Projecto st., 4