SU1246060A1 - Device for tolerance checking of object - Google Patents

Abstract

The invention relates to automation and computer technology and can be used to control processes in various technological objects, such as diesel-electric units of power plants, and allows to increase the reliability of control. The setpoint block 3 forms from the pulse train of the synchronization unit 2 two consecutive binary-decimal setpoint codes corresponding to the lower tolerance limit and the tolerance field, which, through AND 10 and 11, the OR 17 element goes to the adder 6,,; which successively increases the value of the current shift register code 4. When the shift register 4 overflows, the element And 12 and g IJ-N) 4 ;; O) oh smiling

Description

through element 15, the trigger 9 is set to one state, and I register in the shift register 5 is recorded in the lower order. If the monitoring parameter is less than the lower tolerance limit, then the analog-pulse width output at the converter output .. A logical zero, which, through the element NOT 24 and the element AND 14, arrives at the output of the signaling device and through the element OR 20, starts the single-oscillator 7, which returns the device to its initial state. If the control parameter is in the field of the start-up, then the output of the invention relates to automation and computing technology and can be used to control processes in various technological objects, for example, the electric power units of power plants.

The purpose of the invention is the validity of the control.

1 shows a functional diagram of the device for tolerance control of the object in FIG. 2 — the functional diagram of the synchronization unit and the setting unit 5 in FIG. 3 is the time diagram of the operation of the device.

The device for tolerance control of an object contains a converter 1 analog-pulse duration, synchronization unit 2, setpoint block 3, registers 4 and 5, shift, adder b, one-shot 7, triggers 8 and 9, elements AND 10-16, elements OR 17-20, delay elements 21-23, elements NOT 24 and 25, key 26, informational input 27 of the device and two outputs 28 and 29.

The synchronization unit 2 (FIG. 2) comprises a pulse generator 30, a pulse distributor 31, an OR element 32 and output buses 33-36.

Unit 3 settings (figure 2) contains two switches 37 and 38, two elements OR 39 and 40, two outputs 41 and 42.

Information input and transform tel 1 analog pulse duration

Former 1, a logical nlu signal appears that triggers the one-shot 7, thereby resetting the device to its original state. If the monitored parameter exceeds the upper tolerance limit, a second overflow of the shift register 4 will occur and in shift register 5 will be written 1 into the second bit, and from the direct output of the second bit of register 5 this signal will pass to the output of the device and through the key 26 and the OR element 20 - to the one-shot 7, which will return the device to its initial state, ,, 3 Il.

connected to the information input 27 of the device.

The output of the generator 30 pulses of the synchronization unit 2 is connected to the register synchronization input. 4 shifts and with the input of the distributor 31 pulses, the outputs of which (, 2, ... m, where m is the number of decimal bits of the settings) are not connected to the inputs of the OR element 32 of the synchronization unit 2. Outputs: the distributor 3I pulses of the synchronization unit 2 are connected respectively to ko. - mutators 37 and 38 with the inputs of elements OR 39 and 40 of the block 3 of settings, the output of which is connected respectively to the first inputs of the elements AND 10 and 11. The 4th output of the distributor 31 of pulses of the synchronization unit 2 of co3, p. Dinen with the first input of the element And 12 and with zero inputs of the trigger 8 and 9 direct B: The WAYS are connected respectively to the second inputs of the elements 10 and 1 1.

25 The first input of the adder 6 is connected to the output of the element OR 17, the first and second of which are connected respectively to the outputs of the elements AND 10 and I 1.

30 Code sum of the adder 6 is connected to the input of the delay element 21 and the first input of the element And 13, the second input of which is connected by bus 36 to the output of the element OR 32 block 2 si3

chronicity. The transfer output of the adder 6 is connected to the second input element And 12. Information input of the shift register 4 is connected to the output of the element OR 18, the first input of which is connected to the output of the element And 13 and the first input of the element OR 19. The output of the delay element 21 is connected to the second input of the element OR 19, the output of which is connected via delay element 22 to the second input of the element OR 19. The output of the converter is analogous; the pulse duration is connected through the element NOT 24 to the first inputs of the element OR 20 and element AND 14, the output of which is connected to output 28 The output of the one-shot 7 is connected to the control input of the converter 1 analog-pulse impulse, to the reset input of the shift register 5, to the single input of the trigger 8 and to the output of the HE element 25, the output of which is connected to the third input of the I-12 element. The inverse output of the first bit Yes, the shift register 5 is connected to the second input of the AND 14 element and to the nepBbiM input of the AND 15 element, the output of which is connected to the single input of the trigger 9. The information and control inputs of the shift register 5 are connected through the delay element 23 to the output of the And 12 element and the second input element AND 15. The third input element OR 17 is connected to the output element AND 16, the first and second inputs of which are connected respectively to the output of the shift register 4 and to the inverse output of the trigger 8. The second input of the adder 6 is connected to the output of the first discharge of the pulse distributor 31 synchronization unit 2, the 4th output of which is connected to the information input of the one-oscillator 7, the control input of which is connected to the output of the OR 20 element.

The direct output. The second bit of the shift register 5 is connected to the output 29 of the device and to the information input of the key 26, the output of which is connected to the second input of the element OR 20.

The device for the tolerance control of the object works as follows.

The key 26 sets the mode of operation of the device. In the mode of qualitative and quantitative control at the output of the key 26, the signal lo0 acts

0

460604

in the quality control mode of the object, the key 26 connects the direct output of the second bit of the shift register 5 to the second input of the element OR 20.

Consider the operation of the device in the mode of qualitative and quantitative control of the object, when the output of the key 26 is a logical zero signal.

The generator 30 pulses of the synchronization unit 2 produces clock pulses, of which (4in-pa3rd) distributor 31 pulses form 4t sequences of pulses shifted relative to each other by 1 / f time and operating at a frequency f / 4m, where f is the frequency of the clock pulses of the generator 30 pulses; m is the number of decimal places for representation of settings. From the signals 4i-x bits (i-I, 2, ..., t) of the distributor 31 pulses, the element OR 32 forms a sequence

5 pulses operating with a frequency of f / 4.

The block 3 of settings forms from the sequences of pulses of the synchronization block 2 two consecutive binary-decimal codes of settings corresponding to the lower tolerance limit and the tolerance field X, where Xg is the upper tolerance limit.

On switches 37 and 38, the binary codes of the U – X and (Xd-X) codes are set respectively.

For decoding decimal numbers, a 4t-bit binary-decimal code is used, in which every decimal number is encoded by a binary

0 with a tetrade according to the following table: The decimal number is the binary code

0 0000

10001

200 W 3 OOP

40100

50101

601 10

70111 0 -81110

91111

The switches 37 and 38 of the block 3 of the settings in the unit bits of the binary-decimal codes of the settings connect the corresponding outputs of the distributor 31 of the pulses of the synchronization block 2 to the inputs of the elements OR 39 and OR 40, on the outputs of which two

consecutive binary-decimal codes of the settings X and (Xc-X, respectively /

The device starts automatically from the zero signal at the output of converter 1 analog-pulse duration, which, through the elements HE 24 and OR 20, triggers one novibrator 7, forming a single pulse at the output from the pulse sequence of the Ag-th output of the pulse distributor 31 of synchronization unit 2.

A single one-shot pulse triggers a converter 1 analogous to a pulse width, sets the shift register 5 to zero, sets the trigger 8 to one, and blocks the AND 12 element through the HE 25 element.

Converter 1 analog-pulse duration converts an analog signal of a monitored parameter and a pulse signal, the duration of which is proportional to the magnitude of the analog signal at input 27. Pulse signal from an analog converter-pulse duration through the element 24 blocks the element 14 for the duration of its operation.

The trigger 8 in the single state passes the signal from the direct output to the element AND 10, through which the serial binary-decimal installation code 10 X comes from the output of the element OR 39 of the block 3 of settings, to the first input of the element OR 17. At this time, the trigger 8 blocks the AND 16 element with the signal of the inverse output, which ensures erasing the information shifted by the action of the clock pulses of the generator 30 of the pulses of the synchronization unit 2 from the shift register 4. During the operation at the first input of the adder 6, the low-order bit of the binary-decimal code of the setpoint 10. Xj at the second input of the adder 6 a pulse of the first discharge of the distributor 31 of the pulses of the synchronization unit 2 operates. The adder 6 performs successively in time during the time of 4 t, the increment of the set point X of the low-order bit to the initial binary-decimal code, and the sequential binary-decimal result code through delay elements 21 and 22, and the OR elements 18 and 18 19 is written to the register

25

460606

4 shift under the action of the clock pulses of the generator 30 pulses of the block 2 synchronization. Shift register 4 contains the number of bits n 5 4m-2 and is supplemented with elements 21 and 22 of the delay per cycle up to 4 m bit.

After 4 t clocks after being set to one state, the trigger 8 is reset to the zero state by the 4 t pulse of the distributor 31 pulses of the synchronization unit 2.

In the zero state, trigger 8 blocks element 10 and opens element 16, connecting via output 1-SHI 7 the output of shift register 4 to the first input from the armature 6. The current dual decimal code under the action of the clock pulses of the generator 30 the pulses of the synchronization unit 2 are shifted; , starting with a low-order bit, from the output of the register 4 shift through the elements AND 16, OR 17 to the first input of the adder 6, the second input of which during the shift of the least significant bit of the binary-decimal code is acted upon by a p. 3 pulses of synchronization unit 2. Binary adder 6 successively during 4sh cycles increases the value of the current binary-decimal code of the register 4 shift per unit ml: the next digit, and the new value of the binary-decimal code

35 is written from the output of the sum of the adder 6 through delay elements 21 and 22 and elements OR 18 and 19 to shift register 4.

In the future, the device works

0 in the same way, and every 4t clocks the binary-decimal code in shift register 4 is incremented by one. This will continue until the junior tetrad of the current

5 values of the binary-decimal code at the output of the sum of the adder 6 is not formed, the code 1000 (eight). In this case, at the time of the action of a single signal of the fourth bit, the younger tet50 is happy at the output of the sum of the adder 6 and the element 13 is opened, through which, the output pulse of the element OR 32 of the synchronization unit 2 is recorded through the elements OR 18 and 19 respectively into the shift register 4 and element 22 of the delay in place of action, respectively, of the signals of the second and third bits to E: the code of the lower tetrad. Consequently, instead of code 000, code 1110 is written to shift register 4, which corresponds to the decimal eight.

In the next 4 t cycles, the code of the lower tetrad 1110 (eight) is increased by one, and in the 4 shift register, the code 1111 (nine) is written in the lower tetrad, which in the next cycle automatically provides the 1П1 code with the low-order unit of the lower bit. In addition, if the monitored parameter goes beyond the lower tolerance limit, the logic zero signal from the output of the converter 1 is analogous to the pulse duration through the elements NOT 24 and the RSHI 20 to 10 control input of the single-oscillator JfKO that is close The next pulse from a sequence of pulses acting on the 4th output of the distributor 31 pulses of block 2 is synchronized in the adder 6 of the transfer signal from

the fourth bit and the youngest tetrad

for the first discharge of the next tetrad. fs nation Starting the one-shot vibrator 7 air. In this way, the device is reset to the initial state in the described manner, and the device starts to work out the next polling cycle of the monitored parameter at the information input 27.

The numeric count in the .4 shift register is from the initial binary-decimal setup code Y – X. Further calculations in shift register 4 are performed in the same way, and the transfer from one tetrad to the next is done in the same way as the transfer from the npad - neck tetrad in the second tetrad.

This will continue until either the shift register 4 is filled up, or the output of the converter 1 analog-pulse duration does not expire and the logical zero signal is generated, j

If the monitored parameter is X

20

If the controlled parameter X is greater than the lower limit of the tolerance X-, then

shift register 4 is full before the pulse expires

25 signal at the output of the converter I analog-pulse duration. In this case, after the time after the start of the polling cycle (the formation of a pulse at the output of the one-shot 7),

30, at the transfer output of the adder 6, a transfer signal appears from the 4-th bit of the binary-decimal code, which opens AND i, 2. The 4t-bit pulse of the distributor 31 and 30, at the transfer output of the adder 6, a transfer signal appears from the 4t-bit bit of the binary-decimal code, which opens the element And i, 2. The impulse of the 4-th bit of the distributor 31 is less than the lower tolerance limit X,

that the pulse action time at the output 35 of the pulses of the synchronization unit 2, the passage of the converter 1 analogue-pulse duration is less than the time interval Xg-t, where is the cycle of the summation unit in the adder 6; f is the clock frequency of the generator of 30 pulses; m is the number of tetrads of the binary-decimal code setpoint

It goes through the elements of And 12, And 15 and sets the trigger 9 in one state for the time of 4t cycles. The overflow pulse of the shift register 4 formed at the output of the element 12, after a delay time per cycle, flows through the delay element 23 at the information and control inputs of the shift register 5 and is written to

in register 4 shift. In this case, the output of the converter 1 is analogous to And 12, And 15 elements and sets the trigger 9 to the one state for the time of 4 t cycles. The overflow pulse of the shift register 4, generated at the output of the element 12, after a delay time per cycle, flows through the delay element 23 at the information and control inputs of the shift register 5 and is recorded in

the pulse duration is formed in the first discharge. On. the inverse signal of a logical zero, which is the output of the first bit of a 5-shift form - through the element. NOT 24 opens the signal of a logical zero, ment AND 14, at the second input of which are blocking elements AND 14 and 15. Trigger 9 in a single state opens element AND 11, through which the serial binary-decimal code

logical-unit signal

inverse output of the first bit of register 5 shift. The signal of the logical unit, generated at the output of the element And 14, is fed to the first output -28 of the device and can be used50

settings 10 - (Hz - Xj,) from the output of the element OR 40 of block 3 of the setpoint arrives, starting with the low-order bit, to

used to turn on the light or 55 first input of the adder 6.

audible alarm of the monitored parameter leaving the lower tolerance limit, or to enable

46060-8

a gullet that stabilizes the value of the monitored parameter within the tolerance field.

In addition, if the monitored parameter goes beyond the H tolerance limit, the logic zero signal from the converter 1 output is equivalent to the pulse duration through the NOT 24 elements and the RSH 20 to 0 control input of the one-oscillator JfKO that separates the closest pulse from the pulse sequence acting on the 4-th output of the distributor 31 pulses of the synchronous unit 2

20

If the controlled parameter X is greater than the lower limit of the tolerance X-, then

shift register 4 will overflow before the pulse expires

The signal at the output of the converter I is analog-pulse duration. In this case, after the time after the start of the polling cycle (the formation of a pulse at the output of the one-shot 7),

At the transfer output of the adder 6, a transfer signal appears from the 4-th bit of the binary-decimal code, which opens the element And i, 2. 4 t pulse of the distributor of 31 pulses of the synchronization block 2 pass

It goes through the elements of And 12, And 15 and sets the trigger 9 in one state for the time of 4t cycles. The overflow pulse of the shift register 4 formed at the output of the element 12, after a delay time per cycle, flows through the delay element 23 at the information and control inputs of the shift register 5 and is written to

50

settings 10 - (Hz - Xj,) from the output of the element OR 40 of block 3 of the setpoint arrives, starting with the low-order bit, to

The adder 6, as previously described, adds one to the initial setpoint code, and the binary-tenth

9 :

Result code - X) + 1 from the output of the sum of the adder 6 is recorded through delay elements 21 and 22 and the OR elements. 18 n 19 in register 4 shift. Further, the calculations in shift register 4 are performed in a similar manner until either it is again. the shift register 4 is full, or the pulse at the output of the converter 1 analog-pulse width does not end.

If the monitored parameter is within the tolerance field, then at the output of converter 1, the analogue impulse of the pulse produces a logic zero signal before the second overflow of the shift register 4. In this case, the logic zero signal from the output of the converter 1 is analogous to the pulse duration through the elements 24 and OR 20 the one-shot 7 is started, the output pulse of which returns the device to the initial state, and a new polling cycle begins, which is carried out in a similar way.

If the monitored parameter X has exceeded the tolerance limit Xg, then the second overflow of shift register 4 will occur earlier 5 than the impulse signal at the output of the I-analog-to-length converter will expire: pulse value.

In this case, after the time after the start of the polling cycle, the transfer output of the adder 6 shows the transfer signal from the 4-th digit of the binary-decimal code that opens the AND 12 element. The second overflow pulse of the shift register 4 is formed And 12, after a stroke, enters through the delay element 23 on the information and control inputs of the shift register 5, in which the previously recorded first overflow unit is shifted from the first bit to the second, and the second overflow signal is recorded, to the first bit. Thus , at the direct output of the second bit by the shift register 5, a logical unit signal is generated, which is fed to the second output 29 of the device and can be used to load light or sound signaling about the output of the monitored parameter beyond the upper tolerance limit, or to turn on torus, stabilization246060

iO

value of the controlled parameter within the tolerance field. After the second overflow of the 4th junction register, the binary-decimal code of the controlled parameter deviation from the upper tolerance limit begins to form in it. magnitude xx.

D

The binary-decimal code of the value OX-X is formed in register 4 shiftD

the gas for (X-Xg) -t by counting the number of pulses of the first bit of the distributor 31 sh-pulses of the synchronization unit 2, which go to the input of the adder 6. The decimal counting of the pulses is carried out in the circulation circuit of the codes through the adder 6, elements 21 and 22 delays. Prince elements OR 18 and 19, register 4

0 shift, ep and And 6 and OR 17 in the same way.

As soon as a logical zero signal is generated at the output of converter 1 of the analog-pulse duration, the device returns to its initial state, since a single vibrator 7 is triggered through the elements NOT 24 and OR 20, the output signal of which from the output of register 4

0 shift can be read out binary-tic with the code of the value of the variable X-X „number

assessment of the deviation of the monitored parameter from the upper limit of the tolerance field.

5 In the event that the monitored parameter goes beyond the lower limit of the tolerance field, at the moment of the pulse end, a binary-decimal code (X-X) for quantification, a negative deviation of the monitored parameter from the lower one, is generated at the output of the converter 1 analog-pulse duration in the shift offset 4 border floor tolerance which

the signal of the one-shot 7 can be read from the output of the register 4 shift.

Binary-decimal code of quantitative estimates of the output of the monitored parameter beyond the tolerance range for

0 signals of the synchronization unit .2 are read from the output of the shift register 4 and, from the signals from the one-shot 7, are fed to the device of the decal indication or in the digital printing

5 D.PI registration of deviations of the monitored parameter.

Thus, the device performs quality control of parameter 11.

pa, generating signals at outputs 28 or 29 in cases when the monitored parameter leaves the tolerance field, and also calculates quantitative estimates of the deviation of the monitored parameter from the tolerance field boundaries, which are generated as binary-decimal codes in shift register 4 .

If the device is used only for signaling the occurrence of a monitored parameter outside the tolerance field, or a relay control of the monitored parameter. then the polling frequency of the information input 27 can be additionally obtained by connecting the direct output of the second bit of the shift register 5 via the key 26 to the second input of the element OR 20. In this case, the calculation of the quantified estimate of the controlled parameter upper limit of the tolerance field is produced, and the device operates as described, until the second overflow of the shift register 4 is generated.

The second overflow pulse of the shift register 4 from the output of the element I 1 through the delay element 23 is fed to the information and control inputs of the shift register 5, in which the unit

40

the first overflow shifts from the first discharge to the second. The signal of the logical unit of the second bit of register 35 of the shift through the key 26, the element OR 20 starts the one-shot 7, the output of which resets and restarts the converter 1 analog-pulse duration, sets the shift register 5 to the zero state, sets the trigger 8 the unit state and blocks the element AND 12 through the element NOT 25. Thus, the device 45 returns to the initial state and a new polling cycle of the information input 27 begins without spending time on measuring the quantitative assessment of no controlled PA-50 parameters of the upper limit of tolerance floor.

Fig. 3 shows the time diagram of the device operation when the monitored parameter leaves the upper limit of the tolerance field in the quality control mode, when the key 26 connects the control input of the one-vibrator 7 through the OR 20 element

tO fs 20 25

ABOUT

0

5 5 0

24606012

to the direct output of the second bit of the register 5 shift. The time diagram is plotted for positive polarity pulses, the signal of a logical unit corresponds to the upper level, the signal of logical zero is the lower level. Vk, 11Y sum and transfer of the adder 6 are marked on fig.Z respectively S cm 6 and PCM 6.

To represent the settings, one decimal place (t) is selected, and the settings are 7 at and 10 - (XP - at XP 5,.

The distributor 31 pulses of the synchronization unit 2 has four bits, and the output signal of the element OR 32 when coincides with the signal of the 4th bit of the distributor 31 pulses. At outputs 41 and 42, sequential setting codes 0111 (seven) and 1PO (eight) are generated continuously, respectively. As it follows from the time diagram mogi- :, after the upper limit of the tolerance field is exceeded, the logical output signal is generated at the direct output of the second bit of the shift register 5 (1 2p.PC5). The next cycle of polling the monitored parameter of the object starts automatically, since the signal of the logical unit of the second bit of the shift register 5 through the key 26 of the element ШШ 20 starts the one-shot 7, and the polling cycle of the monitored parameter repeats in a similar way. On the time diagram of the output of the converter 1 analogue-pulse duration (PA-DI1), the time intervals corresponding to the bottom X.-t and the tolerance field (Xg-X) х хТ 5 where, f. Are the frequency of the clock pulses of the generator 30 pulses .

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A device for the tolerance control of an object containing an analog-pulse width converter, the first shift register, an adder, two triggers, a synchronization block, a setting block, six AND elements, Tpii delay elements, three i-SHI elements, the first element NOT, and The conversion input of the converter is analogous: the pulse duration is the informative input of the device, the input

13

of the first element is NOT connected to the output of the analogue-pulse width converter, and the output is connected to the first input of the fifth AND element, the output of which is the first output of the device, the second output of the cr-sync block is connected to the second input of the fourth And element, the output group with groups of inputs of the installation unit., the first and second outputs of which are connected to the first inputs of the first and second elements AND, respectively, whose outputs are connected respectively to the first and second inputs of the first OR element, the output of which is connected to The first input of the adder, the overflow output of which is connected to the second input of the third element AND, the output of the sum to the first input of the fourth element AND and the input of the first delay element whose output is connected to the second input of the third element OR. The first input is connected to the direction of the fourth element And, the output - to the input of the second delay element, the output of which is connected to the second input of the second IL element; the first input of which is connected to the output of the fourth element I, and the output to the information input of the first shift register, The second pinholes of the first and second elements And are connected, respectively, with direct outputs of the first and second triggers, the input settings of which are connected to each other, with the first input of the third element And and the output of the higher bit of the last group of outputs of the synchronization unit, that, in order to increase the reliability of the control, a key was inserted in the device, one-vibration

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the torus, the second element is NOT, the seventh element is AND, and the second shift register, the inverse output of the first bit of which is connected to the first input of the sixth element AND and the second input of the fifth element And, the direct output of the second. the bit is with the information input of the key and is the second output of the device, and the reset input is from the control jpe (the converter input is analogous to the pulse duration, with the installation input set to the first trigger state, the input of the second element and the single vibrator The information input of which is connected to the first input of the third element AND, the control input - with the output of the fourth element OR, the second input of which is connected to the information output of the key, the first input - with the output of the first element NOT. It is single with the third input of the third element I, the output of which is connected to the input of the third element of the zadlerski, the output of which is connected to the information and control inputs of the second shift register, the input to the second input of the sixth element I, the output of which is connected to the input of the unit in the second state trigger, the inverse output of the first trigger is connected to the second input of the seventh AND element, the output of which is connected to the third one, the input of the first OR element, the first input to the output of the first shift register, the synchronization input of which th is connected to the first output of the synchronization unit, an output 1ushadshego discharge outlets of the first group which is connected to the second input of the adder,

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Compiled by V. Kopeshov Tehred.Hodanich Proofreader M.Maksimishinets

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for inventions and discoveries 1G3035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

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Claims (1)

Claim Device for tolerance control of an object, containing an analog-to-pulse converter, a first shift register, an adder, two triggers, a synchronization block, a settings block, six AND elements, three delay elements, three OR elements, a first NOT element, and the information input of the converter pulse duration is the information input of the device, the input - 1246060 of the first element is NOT connected to the analog-to-pulse duration converter output, and the output is connected to the first input of the fifth AND element, the output of which is the first output of the device, the second output of the synchronization block is connected to the second input of the fourth AND element, the output group to the input group of the block installations, the first and second outputs of which are connected - 10 yen with the first inputs of the first, second, and second elements AND, respectively, the outputs of which are connected respectively with the first and second inputs of the first OR element, the output of which is connected with the first input of the adder, the overflow output of which is connected to the second input of the third AND element, the output of the sum is with the first input of the fourth AND element and the input of the first delay element, the output of which is connected to the second input of the third IPI element, the first input of which is connected to the output of the fourth AND element , the output is with the input of the second delay element, the output of which is connected to the second input of the second OR element, the first input of which is connected to the output of the fourth AND element, and the output with the information input of the first shift register, in orye first and second inputs of AND gates respectively connected. with direct outputs of the first and second triggers, the input of the installation to the zero state of which 35 are interconnected, with the first input of the third element And and the high-order output of the last group of outputs of the synchronization unit, characterized in that, in order to increase the reliability of control 40, the device is introduced key, one-shot 14, -the second element is NOT, the seventh element And and the second shift register, the inverse output of the first category of which is connected to the first input of the sixth element And and the second input of the fifth element And, the direct output of the second. discharge - with the information input of the key and is the second output of the device, and the reset input - with the control input of the converter, the pulse duration, with the installation input in the single state of the first trigger, with the input of the second element NOT and the output of the one-shot, 15 information input of which is connected to the first input of the third AND element, the control input is with the output of the fourth OR element, the second input of which is connected to the information output of the key, the first input is the output of the first element NOT, the output of the second element is NOT connected n to a third input of the third AND gate, whose output is connected to the input of the third delay element, the output of which is connected to data and control inputs of the second shift register input - to a second input of the sixth AND gate, whose output is connected to. input installation in a single state of the second trigger, the inverse output of the first trigger is connected to. the second input of the seventh AND element, the output of which is connected to the third input of the first OR element, the first input - with the output of the first shift register, the synchronization input of which is connected to the first output of the synchronization unit, the low-order output of the first group of outputs is connected to the second input of the adder, Fig. Gi zo П 1рРИ ~ 31 Г 2рРИ ~ 31 ЗрРЯ-З / Чр рi-jl Ч1БУ ~ 3 Г Ч2БУ ~ 3 L 'LA-DI 1 not 24 goy ~ 7 T' T-8 'Gt-9 ~ and -Yu I-11. PG — 4 or 77 · SCM.6 P See 6 AND? 3- 33-27 OR-19 33 + 2Z or -18 I-72 and-75 'tflpPCS' 'ΰ’Ζρ PCS-J · g ~ g. P___ Fmg.Z