SU1241246A1 - Interface for linking processors with common memory - Google Patents

Abstract

The invention relates to an advanced technique and can be applied in systems in which one memory block is simultaneously used by several processors. The main objective of the invention is to increase the speed when two processors operate with a common memory block. The device contains two triggers, two AND elements, the NAND element, a delay element. 2 Il. iNd 1Y Od

Description

The invention relates to computing technology and can be applied in systems in which one memory block is simultaneously used by several processors.

The purpose of the invention is to increase the speed of the device.

Fig. 1 shows a diagram of the device, and Fig. 2 shows the use of the device together with two processors and a common memory block.

The device (Fig. 1) contains the first 1 and second 2 triggers, the first 3 and the second 4 AND elements, the delay element 5 and the NAND element 6. Figure 2 shows the interface 7, the processors 8 and 9, block 10 memory and multiplexer 11.

The device works as follows. .

Let at the initial moment of time the first trigger 1 is in the state o, while there is no blocking of the first processor 8, and the passage of the synchronization signal from the device Synchronization input to the synchronization output is controlled by the second processor 9. When a request is received from the first processor 8 the request of the device 7, the first trigger 1 enters the state I, which causes a lock on the sync output of the next request from the first processor 8. The request service of the first processor 8 performs the in the absence of a request from the CPU 9. When this locking device 7 to set the potential of the input 1, thereby passing control of the synchronizing signal from the CPU 9 to the clock input to flip-flop device vozlagaets 1 -a multiplexer 11 is conditioned to transmit to the device information memory

from the processor 8.

The second trigger 2 and the first element P 3 ensure that trigger 2 is set to state 1 under the condition that a clock pulse passes through the device 7 under the control of the first trigger 1. The occurrence of potential 1 at the output of the second trigger 2 causes the first 1 and the second to reset. .2 flip-flops, with the delay element 5 resetting the second flip-flop 2 with a delay sufficient for throwing the first flip-flop 1.

If, at the initial time, the first trigger 1 is in state I, the first processor 8 cannot reverse c. the next service request until, in the absence of a request from the second processing processor 9, a synchronizing pulse passes through the device 7, which will drop the first trigger 1 with the falling edge

in state

ON

O. The reset of the trigger 1 in O is carried out by means of the trigger 2 and the element IZ.,.

By setting the potential O at the interlock input of the device 7, the second processor 9. ensures exclusive use of the memory device, while the multiplexer 11 is also configured to transfer information from the processor 9.

The proposed technical solution ensures the operation of one of the processors with shared memory with minimal delay, which is especially important when the frequency of calls of this processor prevails over the frequency of calls of the other. In this variant, the delay dp of the second processor and its value for gating pulses is determined by the speed of one element I. The time taken to register a request from the first processor is determined by the response time of one trigger. If the requests of the two processors coincide in time, the operation of the first processor is suspended until the second processor has a free time window with the memory device. If the second processor is implemented using firmware, the percentage of operations performed on the data without accessing the memory is sufficiently large to combine the operation of the I / O channel and the computing device. At the same time, an increase in speed is achieved due to a more complete combination of operations of working with memory and transferring locks to a device that uses memory less often. The most effective use of the device in specialized systems is task-oriented, with a certain ratio of the percentage of computational operations using memory and operations,

3,

input output. For example, if it is known that all I / O operations can be completed by the required moment using time intervals when the computing device does not access the memory, the I / O will not restrict the computation

Claims (1)

Invention Formula A device for interfacing the processors with a common memory unit containing two flip-flops and two AND elements, the synchronous input of the first flip-flop being connected to the request output of the first processor, the single output of the first flip-flop connected to the information input of the first flip-flop the processor, the first input of the first element I is connected to the first input of the second element I and is connected to the sync output of the second processor, the second input is the first 444. . The second element And is connected to the blocking output of the second processor, the output of the second element And is connected to the synchronous input of the first processor and the common memory block, while the information input of the first trigger is connected to the unit potential bus of the device, the output of the first element II is connected to the synchronous input of the second trigger, characterized in that, in order to improve speed, an AND-NOT element and a delay element are introduced into it, the second input of the second element AND is connected to the output of the AND-NOT element, the first and second inputs of which are connected respectively, with the second input of the first element And the zero output of the first trigger, the zero input of which is connected to the input of the delay element and the output of the second trigger, the zero input of which is connected with the output of the delay element. PTF .; (Put. G Compiled by S. Pestmal Editor L. Pchelinska Tehred O. Gortvan Proofreader E. Sirohman Order 3490/44 Edition 671Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Rauschska nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4