SU1241195A1 - Programmed control device - Google Patents

Abstract

The invention relates to automation and control, and is intended for use in software systems controlling various technological processes, for example, for controlling the production process, of catalysts. The invention allows to extend the functionality by sending control commands to a group of actuators according to a predetermined time (Luc 4 CO SP Watt FIG.}}

Description

a program or when processing and analyzing signals from sensors having a frequency output. When the device is started, the control pulse through the OR 9 element is fed to the input, register 13 and sets it to the first command, from the outputs of register 13 a high level signal is fed to the input of the AND-NOT 12.1 element, preparing it for operation, and the signal is neither: | Whom the level goes to the input 4 of the lAj-a set of programs from its output - to the executive elements 15I ... 15.p. The device operates in one-way modes, which are programmed on the program set block 14. In the first mode — control commands are sent to actuators according to a specified time program — a low level signal from the output of the program set block, 14 prohibits the operation of IZ elements 20 and the code comparison unit 24, as well as through the element NOT 19, allows the operation of elements 44, 21. From the output of the pulse generator 22, the pulses arrive at the inputs of the distributor for a clock time interval of 5, per line. From the second inputs of which, from the output of the block of program set 14, a high-level signal is received that permits the passage of pulses through the element 4 and 4 to the counting input of the counter 6, and from output1

The invention relates to automation and control and is intended for use in software systems for controlling various technological processes, for example, for controlling the technological process of producing catalysts, the peculiarity of which is that the control device, besides sending control commands to actuators, in a given time program, should give control commands after processing and analyzing signals from sensors, frequency output and located on control object

The purpose of the invention is to expand the functional capabilities of the device of the last bit to the counting input of counter 7. From the outputs of counters 6 and 7, the binary-tenth code goes to memory blocks 17, 23, 25, and through matching blocks 11 to the inputs of the setters of codes 10. The pulse shaper 16 prohibits the operation of the memory blocks 7, 23 and enables the operation of the memory block 25. From the outputs of the memory block 25, the code goes to the display unit 26. If the code at the output of counters 6 and 7 and the code dialed. master of codes 10 for the first program, at its output it appears with the signal that goes through trigger 18 and through element NOT 27 through element I-NE 12.1 onto element AND 21. From the pulse generator 16, the interrogation pulse enters through element 21 and through element OR 9 to the input of the shift register 13 and shifts to the second team If a second mode is programmed on the second command — sending commands to the executive device after processing and analyzing signals from sensors that have a frequency output — a high level signal from program set 14 permits operation of elements 3, 20, of the block comparison of codes 24 and prohibits work through the element NOT 19 zlementovI 4, I21.2 Il.

by invoking control commands for a group of actuators according to. specified time program or after processing and analysis of sensor signals with frequency output. .

FIG. 1 is a functional diagram of the device in FIG. 2 - timing diagrams for the operation of the device.

FIG. 2 is indicated: a - output of the distributor — amplifier of the signals of the distributor — amplifier of the signals of the sensors, b — fifth output of the pulse former; in - the output of the divider 1 {g is the polling pulse from the sixth output of the pulse former d. - pulse

3 1241

resetting from the first output of the pulse formation; and - voltage, f - frequency; t - time

The device contains a divider 1, a distributor-amplifier 2 signals of 5 sensors, containing the elements 2.1, ... 2.P, first element IZ, second element AND A, distributor 5 of a clock interval of time, consisting of elements 5.1, .., 5.p, first 6 and second 7 counters, trigger 8, element OR 9, unit setter 10, which includes elements 10.1, i., J.P., matching blocks 11, elements AND-NO 12.1, ..., 12.P, p. Reg. Of shift 13, block of program set 15, 14, actuators 15, pulse generator 16, memory block 17, trigger 18, NOT 19 element, fourth 20 and third 21 elements And, pulse generator 22, 20 and 23 block, code comparison block 24, memory 25, display unit 26, element NOT -27. .

Divider 1, performed on binary.

but-decimal counter, has two counting inputs. At the first input, square-wave pulses are applied, which at a high level permit, and at a low level, they prohibit counting. A second signal is applied to the second input. The rac - preamplifier-amplifier 2 of the sensor signals includes several transistors (not shown) and elements AND 2.1, ..., 2.P (the number of these depends on the number of sensors with frequency output), the outputs of which are combined by OR. The distributor 5 clock interval consists of several elements AND-NOT 5.1, .... 5.p (the number of elements depends on the number of outputs of the pulse generator. 22), the second inputs from the block of program set 14 receive signals that, at a low level, prohibit when high, they allow clock pulses to go to the output of its first inputs, pulse generator 22. Counters 6 and 7 are connected in series and serve to count the number of ticks when working in time mode and percent when working with frequency Sensors. Trigger 8 serves to subtract the initial value of the frequency when working with frequency sensors (since at zero load the output of the frequency sensor has a signal different from zero). Setter 10 codes

5 Ю 15 20

25

5 40 45 50. five

195 4

serves for setting, time interval in clock cycles and signals from frequency sensors in percent (the number of sets of sets of codes 10 corresponds to the number of counters, and the number of sets of codes 10 in a row equals the number of outputs of the shift register 13, i.e. the number of working commands ). The pulse former 16 serves to generate the pulses necessary for the operation of the device. The first 17 and second 23 blocks of memory together with the block of comparison of codes 24 serve to memorize and compare the codes of the post. The counters 6 and 7 received from the outputs. The third memory block 25 together with the display unit 26 serves to indicate the number of taps or the signal from the frequency sensors in percent. The setting units of codes 10 are assembled on standard converters PP 10, the block of program set 14 is on multi-contact connectors such as VG 1H-3, the output blocks 15 are a combination of integrated circuits of the 511 series with a relay

. RES-10 and MKU-48. The remaining blocks. assembled on a series of 511 chips. The device operates as follows.

When the device starts, the control pulse through the OR 9 element is fed to the input of the shift register 13 and sets it on the first command. From the outputs of the shift register 13, the high level signal is fed to the input element AND-NOT 12.1, preparing it. to work, and the low level signal is fed to the input of the block of the program set 14, and from its output through the actuators 15.1, ..., 15.P to the actuators that are not shown (depending on the dialed program).

The device operates in two modes, which are programmed on block 14 of the program. If the first mode is programmed — control commands are sent to actuators according to a specified time programi — the low level signal from the output of block 14 of the program enters the inputs of the AND 3 element, AND element 20, a block of comparison of codes 24, prohibiting their operation, and the input of the element NOT 19, from the output of which the high-level signal is fed to the inputs of the element 4, the element 11, and the gap. Simultaneously with the installation of the shift register 13 on the first command, the operation of the pulse generator 22 is permitted. from the output of which the pulses with different intervals come to the inputs of the distributor 5 clock interval of time (elements AND-NOT 5.1, ..., 5.p), and to one of the second inputs of which from the output of the program set block. 14. A high-level signal is received, which allows the passage of pulses from a selected time interval to the first input of the AND 4 element (for each command on the block of program set 14, any clock time interval can be programmed). From the output of the AND-4 element, the pulses go to the counting input of counter 6, the ac output of the last digit of counter 6 goes to the counting input of the second counter 7. From the outputs of counters 6 and 7, the binary-decimal code goes to the inputs of memory blocks 17, 23 , 25, and through matching blocks 11 - to the inputs of the sensor codes 10, C of the pulse shaper 16 to the inputs of the recording of the blocks of memory 17 and 23 receive signals of a low level and prohibit their operation, to the input of the recording of the memory block 25 receives a signal of the high level “and permits his work. From the outputs of the memory block 25, the code is fed to the input of the display unit 26, from the readings of which it is possible to determine the time from the beginning of the action of this command. When a code coincides at the output of counters 6 and 7 and the code dialed at the setters of codes 1.0 for the first command, a high-level signal appears at its output, which is fed to the input of the element AND NOT 12.1 of the group of NAND elements, and the input of which from the shift register 13 comes a high-resolution signal. At the output of the element IS-NE 12.1 a low level signal appears, which is fed to the third input of the trigger 18, and through the element NOT 27 to the first input of the element 21. In this mode trigger 18 is not involved in the work. From the pulse former 16, the polling pulse (see FIG. 2d) is fed to. the first input element And 21, and from its output through the element-OR 9- to the input of the shift register 13, and produces a shift to the second command. If the second command is programmed with the second mode - the flow of control commands to the actuator

5 jq jq 25 j-

five

0

five

0

five

after processing and analyzing the signals coming from the sensors having a frequency output, a high level signal from the program set block 14 enters the input of the AND 3 element, the AND 20 element, the code comparison block 24, allowing them to work, and the input of the NOT element 19, from the output of which the low level signal is fed to the input of the element And 4, the element And 21, prohibiting their operation. .

For example, consider working with. Weight measuring sensors having. output signal with a frequency of 4000 - 8000 Hz. From the output of block 14 of the set of programs 14, the high level signal goes to the second input of element 2.1 (if work with the first sensor is programmed), and to the second input - the signal from the first sensor. From the distributor-amplifier 2 sensor signals (Fig. 2a), the amplified signal is fed to the input of divider 1. Since divider 1 has a division factor of four, and its first input comes from rectangular pulses with a period of 0.1 c (fig. 26), which, at high level, allow the frequency signal to pass through the divider, and at low, prohibit it, then the total division factor is forty. From the output of the divider 1 signal, 100-200 impulses / s enters the input of the element IZ, and from its output to the counting input of the counter 6. For normal operation, it is necessary to subtract 100 imps, which is triggered 8. After dialing the counters 6 and 7 .100 imp. during the time equal to t (Fig. 2c), the counters 6 and 7 are automatically reset to the zero state and the trigger 8 is set to the single state, i.e. at the output of the trigger 8, a high level signal appears, which hits the input of the trigger 18. Then, during a time of 0.1 s | (tj), the counters 6 and 7 are filled with pulses (100. imp.) the true value of the measured weight. Thus, the range of the measured weight is divided into percentages: 0% corresponds to a frequency of 4000 Hz, 100% corresponds to a frequency of 8000 Hz. Counters 6 and 7 convert the signal 0-100 imp. in binary-decimal code, which through matching blocks 11 is fed to the code sensors.

10 and to the inputs of the memory block 25. To the recording input of the latter from the imaging unit 16, recording pulses are received after a time equal to the period, which update the information in the memory block 25, and the output of its binary-tenth code is fed to the inputs display unit 26, on the basis of which it is possible to determine the weight, expressed as a percentage. If the weight has not reached the programmed value, then the binary-ten code at the output of counters 6 and 7 and the binary-decimal code dialed from the setpoint of codes 10 do not match, and a low level signal remains at its output which arrives at the first input of the elements AND-NOT 12.2 of the second command. At the input of the element H-NO 12.2, a high level signal remains /, which enters the input of the trigger 18 and prohibits its switching. At the output of trigger 18, a low level signal remains, which prohibits the passage of a polling pulse (Fig. 2d), i.e. prohibits the shift to the third team. After passing the polling pulse from the first output of the former 16, a reset pulse is received (Fig. 2 d), which resets the counters 6 and 7 to the zero state, triggers 8 and 18. Then the new filling cycle of the counters 6 and 7 begins and so on until the weight reaches the programmed value.

When the programmed weight is reached, the binary-decimal code at the output of counters 6 and 7 and the binary-decimal code dialed on the master of codes 10 coincide, and a high level signal appears at its output, which is fed to the input of the AND-NOT element 12.2 (second) team. A high level signal is applied to the input of the NAND 12.2 s element. Shift register 13. At the output of the NAND 12.2 element, a 1/0, differential appears. which enters the input of the trigger 18 and switches it to one state.

i.e. the high level signal arrives at the input of the element 20, the input of which from the output of the block of program set 14 arrives at the high level, and its first input from the output of the former 16 receives a polling pulse (Fig. 2d). This impulse through the element AND 20 is fed to the input of the element OR 9, and from it you.

ten

15

20

25

thirty

35

40

45

50

55

the course enters the input of the shift register 13 and shifts the third command.

In this mode (when considering an example of weight measurement), the device monitors the process of weight gain, i.e. determines the weight increment for a specific time interval. For this purpose, serve the memory blocks 17. and 23,. Block comparison codes 24..

The monitoring is carried out as follows.

From the output of counters 6 and 7, the binary-decimal code is fed to the inputs of memory blocks 17 and 23. The first write pulse arrives at the write input of memory block 17 from shaper 16, which at a selected time interval T, equal to the period, produces. code entry in memory block 17, its output is recorded code is fed to code comparison block 24. After a time interval T relative to nei) - a second write pulse to the input of memory block 23 a second write pulse enters the rotor. the memory 23 ac of its output, the recorded code is fed to the code comparison block 24, where the codes are compared at the present and in the future. If the codes match, which indicates the absence of weight gain, then at the output of the "code equalization" block, a high level signal appears that is abnormal. If the codes do not match, which means weight gain, then a low level signal appears at the output of the code comparison block 24, which prohibits the alarm, and the device will continue to work.

. The use of the device allows you to automate the production process and allows you to work with sensors, frequency identification, according to the program, setting any desired parameter value. As a result, a significant economic effect is obtained, energy and labor costs are reduced, the production culture is increased.

Claims (1)

Invention Formula Device for software control, containing two counters,. matching blocks, sequentially middle shift register, program block and executive elements, whose outputs are control outputs of the device, the first and second sets of codes for the number of counters connected by the input-. with the outputs of the blocking units, the first element I, the output connected to the counting input of the first counter, the output of the higher bit of which is connected to the counting input of the second counter, is the pulse former,. the first sensor connected to the fault inputs of the counters, g & pulse generator; 5 second pulses; and the second element I, the display unit, the distributor of clock HHTejiBana time, so that, in order to expand the functionality devices by sending control commands to a group of actuators according to a given time program or during processing. and analyzing signals from sensors having a frequency output, 25 a divider, a distributor-amplifier of sensor signals, three memory blocks, a block compare to rows two .triggera group AND-NO elements and two AND gates and two LP of NOT., an OR gate, pervB. the input of which is the starting input of the device, the outputs of the first and the second; the counters are connected to the inputs of the memory blocks and to the inputs of the first and The second setters of codes. Accordingly, the output of the senior bit of the second counter is connected to the installation input c. 1 of the first trigger, the jump input of which is connected to the first input of the second trigger and to the first, the output of the pulse former, and the single output to the second input of the second trigger, the outputs of the setters of codes are connected and connected to the first inputs of the AND-NOT group, the second inputs of which are connected to the second outputs of the shift register, and the outputs of the AND-HE group are combined and connected to the third input of the second JQ flip-flop and, through the first element, NOT to the first input of the third element I, the first outputs of the generator of pulses are connected to the first inputs of the AND-NES components included in the clock time interval The second inputs are with the second outputs of the program block, and the outputs of the NAND elements included in the clock interval distributor are combined and connected to the first input of the second And element, the second output of the pulse generator is connected to the input of the pulse former, the second, third, the quarter outputs of which are connected to the recording inputs of the corresponding memory blocks, the fifth output is connected to the first counting input of the divider, and the sixth output - to the first and second inputs of the quarter and third elements, And the first inputs are distributed The sensor signal amplifiers are inputs of the frequency signals of the sensors, the second inputs of the distributor amplifiers of the signals of the sensors are connected to the third output of the program block, and the output of the distributor, the signal amplifier, is connected to the first input of the first element And, the second input of which is connected to the fourth output of the program set block, to the input of the NO element, with the second input, the fourth AND element, and with the first input of the code comparison block, the output of the second element is NOT connected to the third input the third element And through the second element And to the output of the first element And, the output of the second trigger is connected to the third input of the fourth element And, the output of which is connected to the output of the third element And and to the second, input of the element OR, the output of which is connected to the counting input of the shift register, the outputs of the first and second memory blocks are connected to the second inputs of the code comparison unit, the output of which is the output of the alarm signal, the output of the third memory block is connected to the inputs of the indication unit.- -. Editor M. Bandura Order 3487/42 Compiled by A. Spravnikova,. Tehred L. Oleinik Proofreader E. Roshko Circulation 836 Subscription, VNIIPI USSR State Committee .on matters of inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d; 4/5 Production and printing company, Uzhgorod, st. Project, 4