SU1239832A1 - Signal synthesizer with tuneable frequency - Google Patents

Abstract

The invention relates to radio engineering. The frequency range of the generated signals is expanded. The synthesizer contains accumulator adder 1, phase to amplitude code converter 2, DAC 3, low pass filter 4, PgdSV three code comparison blocks (BSC) 5, 9 and 10, code setting block (BSC) 6 number of cycles, trigger 7, control block (CU) 8, cycle counter 11, blocks for setting the lower and upper frequencies of the range 12 and 13, UPC 14 frequency increments and the setting unit of the frequency code 15, made in the form of an algebraic adder. In addition to the formation of a periodically varying voltage with a constant oscillation frequency, the synthesizer provides for the formation of a voltage with an oscillation frequency varying according to a given law. Moreover, the law of variation of the oscillation frequency is determined by the sweep speed, i.e. the law (taking into account the sign) of the change in wide ranges of speed, frequency and time (the number of cycles in each time interval) of operation of the synthesizer. The goal is achieved by introducing BSK 5, 9 and 10, BZK 6 and 14, trigger 7, BU 8 and loop counter 11. 2 Il. i (Л 1ч9 со со 00 со

Description

The invention relates to radio engineering and can be used for high-precision measurements and verification of measuring apparatus.

The aim of the invention is to expand the frequency range of the generated signals.

FIG. 1 presents a tunable signal synthesizer circuit with a tunable frequency; in fig. 2 shows an embodiment of the control unit.

The tunable frequency synthesizer contains a accumulating adder 1, a phase to amplitude code converter 2, a digital-to-analog converter (DAC) 3, a low-pass filter 4, the first code comparison unit 5, the code setting unit 6, the number of cycles, trigger 7, control unit 8, second code comparison unit 9, third code comparison unit 10, 11 cycle counter, lower range frequency setting unit 12, upper range frequency setting unit 13 frequency increment setting unit 14, frequency code setting unit 15.

The control unit 8 comprises the initial state button 16, the Start button 17, the OR element 18, the trigger 19 the AND element 20, the delay element 21.

The tuner of signals with tunable frequency works as follows.

The signal from the initial state button 16 at the output of the initial state of the control unit 8 generates a signal according to which the counter 11 is set to the zero state, the outputs of the 9 task code number of the number of cycles form the NU code, the specified number of cycles, at the outputs of the task 14 The increment code generates the D f code of the specified frequency increment at, and the initial frequency code at i 0, i.e. code fg.

At the same time, the setting device 15 of the frequency code is executed in the form of an algebraic adder.

At the outputs of the lower frequency setting unit 12, a code f of the selected lower limit of the frequency range is formed, and at the outputs of the upper frequency setting unit 13, the code fj is generated. selected upper limit of the frequency range, and at the output

five

0

five

0

five

0

five

the adder 1 generates an H code; the selected initial phase at i О, t. e. -.

The second 9 and third 10 comparison blocks carry out a constant comparison of the contents of the f-master frequency code 15 with the f and f codes. At the output of the third comparator block 10, a signal appears at that moment in time when f is greater than f, i.e. with f. f. At the exit of the second

I 8

In block 9, a signal appears if f. S fn For definiteness, we assume that f n Then, after writing the frequency code at the output of the second comparison unit 5 to the generator 15, a signal is received that sets the trigger 7 to the zero state. In this case, the output of the trigger 7 generates a signal of such a level that, arriving at the control input of the setting unit 15 of the frequency code, sets it up for the subsequent summation of codes arriving at the information inputs of the setting unit 15 of the frequency code, i.e. If /, the first comparison unit 5 performs a permanent comparison of the contents of the N of the counter 11 with the specified number N of the frequency sweep. At the output of the first. Block. 5, a signal is generated at that moment in time when the contents of counter 11 becomes equal to or greater than N, i.e. N N. Consequently, in the initial state at the output of the first block, 5 comparison signal does not occur. Converter 2 performs the conversion of the code h. The initial phase (argument) of the periodic function is converted to the code of its instantaneous value Y. Y. DAC 3 cost

There is a conversion of the digital code Y to the equivalent value of the voltage of the electric current U. Ujj. Low frequency & 4 provides a smooth setup of the output signal U (t) U on the decoder bus.

On the Start signal from button 17 and under the action of the clock signals that arrive at the clock input of the control unit 8, the latter generates the clock signals of Clock 1 and Clock 2. These signals arrive at the clock inputs of the accumulating sum-. 55 torus 1 and setpoint frequency code 15 ,. The sequence of clock signals arriving at the clock input of the setting unit 15 of the frequency code is a shift50

that (for the time of transient processes in accumulating adder 1) a copy of the sequence of clock signals arriving at the clock input of accumulating adder 1,

According to these clock signals, accumulative adder 1 implements the code of the current phase value in the form f (2nJ: f. +4) modZTT. Here it is assumed that the period of the reproduced function is normalized by the magnitude 2 IT. Frequency code sensor 15 forms the code of the current frequency of the generated signal in the form of f. C "- d. -I, f. t f j ,, where i is the measure number; i int (t / t-,); t is the current time; c is the period of the clock signals (sampling period).

The converter 2 converts the codes of the current value of the phase of the periodic function into the codes of its instantaneous values Y. D / A converter 3 converts the digital codes Y to their equivalent electric current voltage values Ui. The low pass filter 4 performs low-pass filtering of the stepwise varying voltage formed by the combination of and. i.e. carries out the final formation of a periodically varying voltage U (t).

Pervp 9 and second 10 comparison blocks compare the current value of f- with the boundaries of the frequency range of f selected in this time interval of the device operation. and f. Depending on the results of the comparison, the trigger 7 generates a control signal for addition (4- sign) or subtraction (the sign -), which determines the operation mode of the frequency code generator 15. Since at the initial moment of time it is assumed that f-, o n ° o time point (when f. F) in the unit 15 of the frequency code is added (increase f. To c). After this time point (when f. 9 f), frequency reading is performed in the frequency code generator 15 (decreasing the f value to f), etc. Counter 11 calculates the number of changes in the status of trigger 7 - the total number of cycles N of sweep (sweep) frequency and when this number N reaches the value N specified for this device time response, the first block 5

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The comparison generates a signal by which the control unit 8 brings the signal synthesizer to the initial state for the new time period 5 of the device operation or stops its operation.

The control unit 8 operates as follows.

When you press the button 16 of the original

10 states at the output of the initial state, a signal is generated, which ensures the installation of the signal synthesizer to the initial state. Simultaneously, the signal from the exit button

t5 16 of the initial state, the passage through the element OR 18, sets trigger 19 to zero. The signal from the output of the trigger 19 blocks the passage of clock signals through

20 element And 20 at the first and second (via element 21 of the delay) clock outputs.

When you press the Start button 17, a signal is generated that translates

25, the trigger is triggered, and the clock signals begin to flow to the corresponding outputs of the control unit. If at some point the first comparison block 5 generates a signal,

0 then it passes through the element OR 18 and sets trigger 19 to zero.

Each of the blocks of setting the code for the number of cycles 6, the setting of the lower 12 and upper 13 frequencies, block 14 of the task

5, the increment code works in such a way that, by signals received at its inputs from the control unit 8, a code is first generated at the output of the switch unit (it can be understood

0 yrpQ this control signal forms the operator by dialing the required code on the software switch), and then this code is rewritten into a register (the switches and register are not shown).

Thus, the introduction of new functional blocks and expands the capabilities of the known device. In the proposed signal synthesizer with a tunable frequency, in addition to the formation of a periodically varying voltage with a constant oscillation frequency, a voltage is formed with a frequency of oscillations changing according to a given law. Moreover, the law of variation of the oscillation frequency here is determined by the sweep speed, i.e. the law {taking into account the sign of change in wide ranges of speed and frequency of Stot and time (the number of cycles in each time interval) of the device’s operation,

In contrast to the known device in the proposed device, the range and: changes the sweep speed (towards its upper boundary) is expanded and ensures the discreteness of the frequency sweep speed setting.

The range of variation of speeds in the case of using the code 15 code as a sensor. The frequency of an algebraic adder can be ensured by increasing the algebraic size of the matrix from f to f bits. This is much easier to implement than the use of a controllable divider frequency control as a master of frequency code 15.

Thus, the advantage of using the frequency code of an algebraic adder as a generator 15 is that the discreteness of setting the sweep speed is constant over the whole range and the sweep speed is proportional to the code uf. in the block set the increment code.

Ф о р. m l l a and 3 o b ete n i o

Signal synthesizer with tunable frequency, which contains serially connected frequency code adjuster, accumulates 1n 1: th sum generator, converts the cause of the phase code into aa Sh. Liter, pifroanalog converter.and filters them frequencies, and task blocks .1 of the lower and upper frequencies of the range, with this input setting the initial state of the frequency code setter is the input setting the initial frequency of the signal synthesizer with the fixed frequency, which is the same. In order to expand the frequency range of the formed CHrHanoBj 3, the control unit

The lines connected in series 6.POK set the code for the number of cycles and the first block of code comparison, sequentially connected the second block of code comparison, trigger and cycle counter, the third block of code comparison to the block for setting the frequency increment code; Frequencies are made in the form of an algebraic adder, the inputs of setting the initial connection neither the setpoint of the frequency code, the accumulating adder, the setting block for the lower frequency range, the setting block for the upper frequency range, the counting of cycles, the setting block for the increment code Frequency and code block for the number of CYCLES are combined and connected to the output of the initial state of the control unit 5 whose signal input is connected to the input of the first comparison unit, the first and second clock outputs of the control unit are connected respectively to the clock input of the accumulating adder and to the clock input of the frequency code setpoint , E; The progress of the increment of the code of the frequency of which is connected to the output of the block of the task of the code of frequency appraisal, p.p-) for. the group of inputs of the second block of CABLE codes and the first group of inputs of the third block of code comparison units are combined and connected to the code output of the frequency code setter; code outputs of the lower frequency range setting unit are connected to the second group of inputs of the second code comparison unit; the range is connected to the second group of inputs of the third block of code comparison, the output of which is connected to the second input of the trigger, the output of which is also connected to the control input of the frequency code, and the code vy output score snip cycles connected to the second group of inputs of the first comparator unit. at ztom clock input of the control unit is a clock WMOs Tzom signal synthesizer tunable.

; fc A. comp.

Tacts 2

Editor A. Shandor

Order 3407/55. Circulation 816 Subscription

VNISh of the USSR State Committee for Inventions and Discoveries. 113035, Moscow, Zh-35, Raushsk nab. 4/5

Production and printing company, Uzhgorod, Projecto st., 4

2

Compiled by Y. Kovalev Tehred O. Sopko

Corrector. And, Obrukhar

Claims (1)

A signal synthesizer with a tunable frequency, containing a series-connected frequency code master, an accumulating adder, a phase-to-amplitude code converter, a digital-to-analog converter, and a low-pass filter, as well as low and high frequency range setting blocks, while the input of setting the initial state of the frequency code setter is an input setting the initial frequency of the signal synthesizer with a tunable frequency, such as that with that. in order to expand the frequency range of the generated signals, a control unit, series-connected code setting unit for the number of cycles and a first code comparison unit, series-connected second code comparison unit, a trigger and a cycle counter, a third code comparison unit and a task unit are introduced into it frequency increment code, while the frequency code master is in the form of an algebraic adder, the inputs of the initial state of the frequency code master, the accumulating adder, the low frequency range set unit, bl to set the upper frequency of the range, cycle counter, block for setting the frequency increment code, and block for setting the code, the number of cycles is combined and connected to the output of the initial state of the control unit, the signal input of which is connected to the output of the first comparison unit, the first and second clock outputs of the control unit are connected, respectively to the clock input of the accumulating adder and to the clock input of the frequency code setter, the input of the frequency code increment of which is connected to the output of the frequency increment code job block I am the group of inputs of the second block of code comparison and the first group of inputs of the third block of code comparison are combined and connected to the code output of the frequency code sensor, the code outputs of the low-frequency range reference unit are connected to the second group of inputs of the second code comparison block, the code outputs of the task block the upper frequency range is connected to the second group of inputs of the third code comparison unit., the output of which is connected to the second input of the trigger, the output of which is also connected to the control input of the frequency code setter, and the code The new output of the cycle counter is connected to the second group of inputs of the first comparison unit, while the clock input of the control block is the clock input of the signal synthesizer with a tunable frequency.