SU1234966A1 - Digital fpequency synthesizer - Google Patents

Abstract

This invention relates to the field of radio engineering. Increased speed. The device contains an impulse-phase detector (IFD) 1, a low-pass filter 2, a tunable rr 3, a mixer 4, a frequency divider with variable coefficients. division (DCFD) 5, digital frequency detector 6, digital integrator 7, buffer register 8, D / A converter 9, rf of reference frequency 10, frequency multiplier 11. The goal is achieved by introducing serially connected 1 down counter 12, 1 decryptor 14 , EL-OR 16, D-trigger 17, I-to-trigger 18, 2nd subtractive counter 13, 2nd decoder 15, code analyzer 19, switch 20. When changing coefficients. dividing the DCFK 5 during operation of the frequency auto-tuning ring (CPAP) sets the operating point of the IFD 1, is close to the steady-state equilibrium point of the CCAP, which eliminates repeated testing of the CVC of voltage changes at the output of the IFD 1 and sharply reduces the transient error in the ring auto-tuning, which reduces the frequency setting time and increases the speed of the device. 1 il. (L

Description

TiaxoflHTCfi: in mode as long as it is down to zero. This is from the subtracting counter but the second state decoder, the output is the pulse, which is the input of the K-1-K-trigger element OR 16 and passing 17 and will record the BbfM signal into the output of the D-trigger pulse, which is written 18 the state of the decision to record the second gTZ recorder the incoming signal and the trace to it will be recorded

In this case, the impulse to the decoder is 15

Pervts subtracted to produce la N, one for

The invention relates to a radio engineering device and may be used to form a grid of stable frequencies in transceiver measurement equipment .5

The aim of the invention is to increase speed.

The drawing shows a structural electrical circuit of a digital frequency synthesizer.

Digital synthesizer -speed contains a pulse-phase detector (IFD) 1, a low-pass filter (LPF) 2, a tunable generator 3, a mixer 4, a frequency divider with a variable 55 division factor (DDC) 5, a digital frequency detector 6, a digital integrator 7, buffer register 8, Digital to analogue converter (CDL) 9, Reference frequency generator 10, 20 frequency multiplier 11, first subtraction counter 12, second subtractive counter 13, first decoder 1A, second decoder 15, element 1-ШИ 16,

The C-trigger 17, the IK-trigger 18, the analysis-25 continues until code 19, the switch 20.

The digital frequency synthesizer works as follows.

A digital frequency synthesizer consists of three parts: a frequency auto-tuning ring consisting of a tunable oscillator 3, a mixer 4,: a PDA 5, a digital frequency detector 6 and a digital integrator 7, a buffer register 8 and a DAC 9, a phase locked loop, consisting of a tunable generator 3, a mixer 4, a PDKD 5, a switch 20, an IFD 1 and a low-pass filter 2; the IFD 1 reference signal generating unit, consisting of the first and second subtractive counters 12 and 13 of the first and second decoders, 14 and 15, the OR element 16, the D-flip-flop 17 and the 1-K-flip-flop 18.

The formation of the reference signal IFD 1. occurs as follows.

The signal from the output of the reference frequency generator 10 goes to the clock inputs of the first and second subtracts 1x1 counters 12 and 13, the information inputs of which are given constant codes N, and N., respectively. Let him not

35

And N, respectively, that the instant of time the IK-trigger 18 is in state 1, then the signal from its output gives permission to write the code N in parallel to the first subtractive counter 12. The second subtractive counter 13 at this time

reference frequency and

keeping the first novice 12 will not reduce the code of the first deshits pulse, p tilts 1 -Ma goes to the outcome. As a result, the output of the second decryptorically appears in one period o and with a period- equal to the periods of the reference part than between impulses shift equal to (N, - + output pulses of the first 14 are decoded for reading to zero one cycle per delay 17), and equal to (output impulses of go de-diffractors. We analyze to exclude the bot of the circuit.

In the synchronous auto-tuning mode, the switch 20, and the output time of the DCD 5, is equal to la at the output of the second

40

50

55

„

where is noah

g (

"IS n N ,,

1 frequency frequency 10.

TiaxoflHTCfi: in subtraction mode until its content decreases to zero. This state of the second subtractive counter 13 is fixed by the second zero state decoder 15, at the output of which a pulse appears, which is fed to the input of K-1-K-flip-flop 18, and through the OR element 16 it passes through I) -trigger 17 and will be a bbfM signal is written into it, as a result of which a pulse appears at the output of D-flip-flop 17, which writes O-state into 1-K-three ger 18, and an enable signal is sent to the write enable input of the second subtracting counter gTZ the next clock pulse will be written the number N,

Thus, the impulse on the input of the second decoder 15 is completed.

Pervts subtractive counter 12 begins to subtract from the number N, one for each period

continues to those

reference frequency and this work i work

until the contents of the first subtractive counter 12 decrease to zero, and in the code of the first decoder 14 a pulse does not occur, as a result of which the 1 -K trigger 18 is tilted and the circuit returns to its original state. As a result, the outputs of the first and second decoders 14 and 15 periodically appear pulses with a duration of one period of the reference frequency and with a period equal to (N, + N, 4-2) periods of the reference frequency (cycles), and between pulses a time shift equal to (N, - + 1) cycles between the output pulses of the second 15 and first 14 decoders (N, cycles to read zero numbers N plus one cycle per delay in D - flip-flop 17), and (1) cycles between the output pulses of the first and second deshftors. The trigger mechanism 17 is necessary to eliminate the OTE scheme.

In the synchronization mode, the phase locked loop is closed through the switch 20, and the signal frequency at the DPDK 5 output is equal to the signal frequency at the output of the second decoder 15 and receives its nominal value.

„

where is noah

g (

"IS n N ,, 1

1 frequency frequency 10.

generator support312

On the first digital qacTOTfforo detector, at the time of the arrival of the next impulse from the output of the DPCD 5, the zero code will take place and the contents of the integrator 7 will not change. The code analyzer 19 generates an output signal if the output of the c1-fry frequency detector 6, the number N does not exceed in magnitude a certain predetermined value (for example, f may be equal to one or two binary units depending on the system parameters.) In the synchronization modes of the phase locked loop The value N is zero and the output of the code analyzer 1 9 prohibits overwriting the number from the output of the digital integrator 7 in the buffer register, keeping its output code constant, and, accordingly, the output voltage 1DAP 9, as well as connecting the output of PDKD 5 with input IFD.1 through switch 20, the circuit closes the phase locked loop. This state of the device is preserved until the change in the division coefficient in DCPD 5,

When the division factor of the KDP changes, D 5, the frequency of the signal at its output changes and at the output of the digital frequency detector 6 a number significantly different from zero appears, as a result of which in the code analyzer code 19 the signal disappears. In this case, the switch 20 breaks the phase locked loop and closes the frequency locked loop by removing the prohibition of correspondence from the input of the buffer register 8. In this mode, the signals from the outputs of the first and second decoders 14 and 15, the same, frequency, but shifted in time (and, therefore, the p-phase) by an amount determined by the ratio of codes N, This ratio can always be chosen such that the phase shift of the signals at the inputs of the IFD 1 exactly (with an accuracy of one period of the reference frequency ) complied with p IFD bochey point 1 in synchronization FAP ring.

W; boron the ratio of codes N and N can always be ensured that c. the mode of operation of the frequency-locked loop, the phase difference at the inputs of the IFD 1 corresponded to the phase difference in the synchronism mode of the phase-locked loop, which is equivalent to

that the direction at the output of F, CI in both cases remains the same.

If we denote by K oTHonieu, ie, the reference frequency f to the pitch of the synthesizer grid (to the frequency at the second input of the IFD I, then to fulfill this condition, it suffices to choose the values of K ,, and N closest integers to the following values:

f

N, -f.

(ABOUT

N, K (1- -f) -1 ..

(2)

0

five

For example, if a sawn-shaped phase detector is used and the initial detuning is zero, .to, 71 and N, K / 2-1, K / 2-1,

With a triangular characteristic of the phase detector p, 1/2 and NY K / 4-1, N ZK / 4-1.

Thus, in the mode of operation. frequency locked loop rings at the output of the FDI 1 maintains with a constant. After the transient process in the frequency-locked loop is completed and the frequency of the signal at the DPDC 5 output becomes close (to the accuracy of the discrete frequency of the digital frequency detector 6) to its nominal value, the number at the output of the digital frequency detector 6 becomes equal to zero, close to zero, code analyzer: 19 generates an output signal, which opens up a circuit of a frequency automatic frequency tuning loop through an iufer register S with memorization, for example. at the output of the D / A converter 9 and closes the phase-locked loop, connecting the first input of the IFD 1 to the output of the PDKD 5 via the switch 20. At the same time, since the phase difference at the inputs of the IFD 1 was already very close to the steady-state equilibrium point, then the transient the FAP ring has a very small amplitude and duration (the experiment shows that, at K 50, the phase error emission does not exceed 3.5 °),

In the proposed device, when changing the division factor in the PDDK 5 (i.e., when the frequency of the synthesizer is tuned), the operating point of the IFD 1 is set at the time of the frequency-controlled loop, very close to the point of stable equilibrium of the phase-locked loop, which eliminates the possibility of reworking frequency locked loop

voltage changes at the output of the FDD 1 and the transient error in the phase-locked loop is sharply reduced, which ultimately reduces the frequency setting time and improves the speed of the frequency synthesizer. To ensure this effect, it is necessary to set the values of the N, and N codes by formulas (1) and (2) depending on the parameters of the synthesizer and the type of IFD 1 used.

Use of the invention in digital. If you use the first frequency synthesizers, you can eliminate the change in the output voltage of the IFD 1 during the initial frequency setting, set the working point of the IFD 1 in advance, eliminate the possibility of frequency repetitions with the frequency-controlled loop and reduce the transient error in the phase-locked loop, which, in aggregate, improves one of the The main parameters of wideband frequency synthesizers are the speed when frequency tuning.

Claims (1)

Invention Formula A digital frequency synthesizer containing a serially connected pulse-phase detector, a low-pass filter, a tunable generator, a mixer, a frequency divider with a variable division factor, a digital frequency detector, a digital integrator, a buffer register, and a analog converter, the output of which is connected to the second input of a tunable gene. Editor K. Voloshchuk Order 2990/58 Compiled by Y. Kovalev Tehred O.Gortvay M.Samborska Proofreader Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35., Raushsk nab. 4/5 Production and printing: enterprise, Uzhgorod, Projecto st., 4 RATOR, which are connected sequentially to the reference frequency generator and frequency multiplier, the output of which is connected to the second input of the mixer, while the output of the reference frequency generator is also connected to the clock input of the digital frequency detector, which is characterized by the fact that in order to improve performance, serially connected the first subtractive counter, the first decoder, the element OR, the D-trigger, 1 -k trigger, the second subtractive counter and the second decoder, a code analyzer and a switch whose control input is combined with the input of the prohibition of the recording of the buffer register and connected to the output of the code analyzer, the input of which is connected to the output of the digital frequency detector, clock inputs of the first and second subtractive counters and T) -trigger are combined and connected to the output of the reference frequency generator, the first input of the switch is combined with the I input I is a trigger and is connected to the output of the first decoder, with the first input of the pulse phase detector, the input of the T-K trigger and the second input of the OR element are combined and connected to the output of the second decoder, direct out d 1 -K-flip-flop is connected to the enable input of parallel recording of the first subtractive counter, the output of the switch is connected to the second input im-. a pulse-phase detector, and the second input of the switch is combined with a clock input of the buffer register and connected to the output of a frequency divider with a variable division factor.