SU1234851A1 - Multichannel device for processing initial data - Google Patents

Abstract

The invention relates to computing and can be used to collect and process information with a pulse frequency representation. The aim of the invention is to increase the processing speed. The device contains a synchronization block I, a channel switching block 2, a linearization block 3, a coding block 4, made in the form of a counter, a scaling block 5, a memory block 6 - fr I-I (L

Description

1HE

with

4 00 ate

ti, block 7 comparison, block 8 output. The inputs of the channel switching unit 2 are connected to the input of the device, the control input of the unit 2 is connected to the output of the synchronization unit 1, another output of which is connected to the control input of the coding unit A, to the control input of the linearization unit 3 and to the control input of the 7 comparison unit. The synchronization unit is connected to the memory unit 6 and to the comparison unit 7, the output of which is connected to the control input of the output unit 8 and to the input of the memory unit 6, information output

The invention relates to computing and is intended to collect and pre-process information with a frequency-pulse form of representation.

The aim of the invention is to increase speed.

FIG. 1 is a block diagram of the device; in fig. 2 is a diagram of the devices a-with examples of the implementation of the blocks included in the device; in fig. 3 diagram of the analysis unit; in fig. 4 is a diagram of a decoder of the boundaries of the approximation areas and the coefficient memory node.

The device contains a synchronization unit 1, a channel switching unit 2, a linearization unit 3, a coding unit 4, a scaling unit 5, a memory unit 6, a comparison unit 7, an output unit 8, a frequency divider 9, shapers 10 and 1 rectangular pulses, a distributor 12 pulses, formers 13 and 14 rectangular pulses, dispenser 15 pulses, formers 16 rectangular pulses, elements 17 AND, element 18 OR, delay element 19, counter 20, elements 21 AND, element 22 OR, buffer memory node 23 , node 24 for division factors, decoder 25 boundaries of approximation plots: counter 26, elements 27 AND, registers 28, element 29 AND, elements 30 OR, analysis node 31, decoders 32,

which is connected to the information input of the comparison unit, the output of which is connected to the input of the output unit, the output of which is the output of the device, the clock input of the device is connected to the input of the synchronization unit 1. Scaling unit 5 may be implemented as a frequency divider or frequency multiplier. In the device, such operations as scaling, linearization, coding, data compression are performed directly in the measurement process in one measurement interval. 3.p. 4 il.

0

five

0

,

 counter 33, rectangular pulse shaper 34, register 35, .. matching node 36, element 37 OR, delay element 38, trigger 39, element 40 AND, decoder group 41, element P11Sh 42, counter 43, reprogramming memory 44 , 45 frequency multiplier, element 46 I.

The device works as follows.

The inputs of block 2 receive signals in a frequency-pulse form, either directly from the primary transducers (frequency sensors) or transducers., Providing intermediate conversion of the signal from the sensor to the pulse frequency. The unit 2 performs by means of the drivers 16 to match the input signals with the levels received in the device as operating ones. According to signals from the synchronization unit, unit 2 performs a sequential (cyclic) polling of the monitored channels. Unit 1 sets the polling time (T ,,,,) of each channel, the sequence of polled channels and provides general synchronization of the device operation. The clock frequency f, which ensures the synchronization of the operation of this device with the devices performing the further processing of information (for example, a computer), comes from the latter through the clock input of block 1 to the remote controller H

frequencies, at the output of which the pulses have a period of following T ,,. These pulses are fed to the input of the distributor 15 of block 2, the signals from the output of which control the elements 17 of block 2, and to the input of the former 10. The formers 10, 11, 13, 14, the distributor 12 of the block ensure the formation of a sequence of control pulses which synchronize the operation of the device as a whole, namely: shaper 10 — installation of the node 31 of the comparison unit 7; shaper I1 - shift of distributor I2 of block 1 and shift of distributor 15 of block 2, shaper 13 - resetting the counter 26 of block 4, counter 33 of comparison block 7, counter 20 and memory block 23 of block 3, shapers 14 - rewriting co holding one of the registers 28 to the counter 33 of the comparison block 7. The pulse sequence T of the next polled channel through the open element 17 AND and the element 18 OR block 2 enters block 5, where it normalizes (either division or multiplication, which is determined by the problem to be solved). The normalized pulse sequence p is fed to the input of block 3, where it simultaneously arrives at the counting input of counter 20 and through delay element 19 to element 46 I. Pulse sequences are formed at the bit outputs of counter 20. These frequency samples are fed to the inputs of the corresponding elements 21 I, which, together with the element 46 I, are controlled by the inputs by signals from the memory unit 23, consisting generally of control triggers. The order of switching on control triggers (memory node 23) is determined by the nonlinearity nature of the primary converter. The approximation portions (i.e., the moments of the introduction of the correction) of the characteristics of the primary converter are calculated in advance. The decoder 25 of block 3 is a diode array with which numbers are obtained that correspond to the break points of the approximating broken line. In accordance with a predetermined linearization program, the function of converting primary transducers is corrected by adding pulses or subtracting them from

source sequence. In the general case, the corrected pulse sequence dp of primary transducers having a convex characteristic looks as follows:

F; F; 4 g; / 2 + ...- lp; / 2

For primary transducers with a concave characteristic, the corrected pulse sequence is in the form

F F - F / 2 - ...

Thus, the linearization operation does not require additional time and is carried out simultaneously with the encoding process.

Before the next channel is polled, the value of the previous measurement: (if it was informative) or the result obtained on the (iK) -M cycle of the device operation by a signal from the driver 14, is entered into the counter 33 of the comparison unit 7 from the corresponding register 28 of the memory 6 in the additional code. Then, for a time equal to the measurement interval 1,, from the output of block 3 to the input of counter 33 of block 7, the pulse sequence F ,, (t) is received. In this case, the current value of the code generated in the counter 33 is determined by the expression

“- J (t) Jt.

about

the end of T, a code will be generated

By the time of the end of T., in the counter

N

Additional

h 7

- F: (t) jt

given that the summation for the direct code is equivalent to the subtraction for the additional code, the last expression can be rewritten as

Nj5 dop d.

F; (t) j t

Thus, in the counter 33, the modulus of the difference of two samples is formed.

uNj., N i - l - N i.

Decoders 32, made in the form of multi-input elements AND, are tuned to the value of allowable values -Z and + Z. At the same time, one decoder is connected to the corresponding inputs of the direct code of counter 33 and highlights the moment of transition of the signal F (t) of the admissible value - Z, and another decoder connected to the corresponding outputs of the return code of counter 33, selects the transition moment with the signal F (t) of the tolerance + Z,

The outputs of the decoders 32 are connected to the first and second inputs of the node 31 analysis. Thus, if the results of the i-ro and (L-l) -ro ticks are equal, then the code in the counter 33 at the time of the end of Tj ,, is zero. At the same time, era ™ bathes the first decoder 32, since it is set to the code -Z, which is different from zero. The signal from this decoder through element 37 OR triggers trigger 39, thereby closing element 40 AND; if none of the decoders is triggered, then element 40 AND is open, if both decoders are triggered, then trigger 39 is tilted twice and element 40 is open again. The outputs of the trigger 30 of node 31 are connected to the inputs of the decoders 32, which eliminates false alarms. The signal blocking is removed after the signal at the decoder output is generated, which, taking into account the operation of block 7 with symmetrical tolerances, does not violate the performance of FDI comparison.

The content of the counter 33 of block 7 decreases to zero, and then with the very first pulse after zeroing the counter is set to one. If F (tf) F; (t,.,) -Z, then not

none of the decoders works. When satisfied

R; (H, (t.) F; (t ..,) z

-2 decoder works. Under the condition of T (t;) F (t;) + Z, both the -Z and + Z decoder are triggered.

to 15

20 30 5 0

0

five

At the time of the end of the polling of the sequential j-ro channel, the generator 10 of the synchronization unit 1 generates a pulse, which is fed to the input of the element 40 AND of the node 31 of the comparison unit 7. If the signal F (t) has gone beyond the limits of -Z or + Z, then the pulse from the output of element 40 And node 31 goes to the synchronous input of the j-ro register 28 of memory block 6. In this case, the j-th register 28 of memory block 6 rewrites the contents of counter 26. The signal from element 40 AND of node 31 also enters the driver 34, the pulse from which output allows overwriting the next measurement code and the code of the polled channel to register 35 of block 8. At the same time, the signal from the imaging unit 34 through the node 36 of the matching arrives at the output of the device, signaling its readiness to release information (i.e., a ready signal is set).

Block 8 provides the interface of this device with devices that further process information, such as display devices.

At the end of the measuring interval of the pulses from the imager 13 of the block 1, the counter 26 of the block 4 is installed, the counter 33 of the block 7 is comp. unit 23 of the memory and counter 20 of block 3, i.e. The device is being prepared for further operation.

Thus, by the end of each measurement interval, the device performs operations such as scaling, linearization, encoding, data compression. The listed, processing operations are performed directly in the process of measuring j, which allows building high-speed real-time information-measuring systems on the basis of this device, since the principle of distribution of computational power over various levels is realized.

Claims (2)

1. A multi-channel device for processing primary information, a co-switching unit, the information inputs of which are the information inputs of the device, the control input is connected to the first output of the synchronization unit, and the output is connected to the input of the scaling unit, the first information input of the comparison unit is connected to the output of the memory unit, the synchronous input of which is connected to the second output of the synchronization unit, the output of the comparison unit is connected with the control input of the output unit, the output of which is the output of the device, it is intended that, in order to improve speed, a linearization unit and a coding unit, implemented in the form of a counter, are inserted into it The first and, second information input of the comparison unit are connected to. the output of the linearization unit, the first information input of which is connected to the output of the scaling unit, the installation inputs of the comparison unit, the linearization unit and the counter are connected to the third output of the synchronization unit, the quarter output of which is connected to the comparison input of the comparison unit, the output of which is connected to the write enable input of the block the memory whose readout input is connected to the fifth output of the synchronization unit, the output of the counter is connected to the second information input of the nonarisation block and to the info mation inputs of the memory block and outputting the block syn-  „U. a clock input of which is connected to a second output of a synchronization unit, the input of which is the clock input of the device. 2. A device according to claim 1, characterized in that the linearization unit comprises a buffer memory node, a counter, a delay element, an AND element group, an AND element, an OR memory, a coefficient memory node, and a decoder for the boundaries of the approximation regions whose input is the second the information input of the block, and the outputs are connected respectively to the address input and the write input of the reading of the coefficient memory node, the output of which is connected to the information input of the buffer memory node, the installation input of which and the installation input of the counter are connected to The main input of the block, the outputs of the bits of the buffer memory node are connected respectively to the first inputs of the AND element and the elements of the group, the outputs of the AND elements of the group are connected respectively to the inputs of the OR element whose output is the output of the block, the second inputs of the AND elements of the group are connected respectively, with the outputs of the bits of the counter, the counting input of which and the input of the delay element are connected to the first information input of the block, the output of the delay element is connected to the second input of the element I. R (rig. 3 From 26 Compiled by A. Jerenov Editor M. Tsntkina Tehred M. Hodannch Proofreader A. Tsko Order 2987/52 Circulation 671 Subscription BFIHHflH of the USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production polygraphic (: some enterprise, Uzhtor, Proektna str., A