SU1233201A1 - Device for reception and processing of redundant signals - Google Patents

Abstract

The invention is intended for use in information transmission systems for receiving and decoding: i a whole composite redundant signals using long and extra long robust noise codes. The invention improves the robustness of the device by forming the aggregate most likely (L

Description

error vectors in the case when the error vector estimate corresponds to the multiplicity of the maximally correctable error. The device contains a demodulator 1, a memory block 2, a threshold element 3, a decoder 4, error correction, a register block 5, a control signal generator 6, a register 7, a register block 8 executed on the registers 9, an adder 10 modulo two; , decoders 11, 12, detecting errors, the element OR 13, the analyzer

The invention relates to telecommunications and can be used in information transmission systems for receiving and processing in general composite redundancy signals, formed on the basis of long and super-long error-correcting codes.

The purpose of the invention is to improve the noise tolerance of the device.

The drawing shows a structural electrical circuit of the device for receiving and processing redundant signals;

The device contains analogue de modulator 1, memory block 2, threshold element 3, second decoder 4, error correction, register block 5, control signal generator 6, register 7, register block 8, executed on registers 9, an adder 10 for modzshu two, first and third decoders 11 and 12, detecting errors, the first element OR 13, an analyzer 14, executed on the block 15 elements And, register 16, the adder 17 and the threshold element 18, the second element IPI 19, key 20, trigger 21, element 22, the first driver of 23 pulses, executed on counter 245 de the encoder 25 and the register 26, the generator 27 clock pulses of the second shaper 28 pulses on the generator 29 clock pulses S trigger 30 and the counter 315 and the delay element 32.

The device works as follows.

14, executed on block 15 elements AND, register 16, adder 17 and threshold element 18, element OR 19, key 20, trigger 21, element AND 22, driver of 23 pulses, executed on counter 24, decoder 25 and reg-switch 26, a clock pulse generator 27, a pulse driver 28, executed on a clock pulse generator 29, a trigger 30 and a counter 31, and a delay element 32. 2z.p. 5 1 il.

A composite signal with redundancy from the communication channel enters an analog demodulator 1, in which it is converted into an output set of difference elementary signals X (x, x 00.Xj), where H is the number of elementary signals in the composite redundant signal or the number of binary signals in code signals combinations of The analog combination X is stored in memory block 2. Next, the elementary analog signals X are fed to the input of the threshold element 3, which converts them into binary symbols aj (i 1, H), These binary symbols a. form a binary code combination A (a,, a, .., a,), which goes to decoder 11. If no error is detected in decoder 11, i.e. the combination A is an allowed code combination, it is output to the device output through the OR element 1, after which all the blocks are reset, and the device is ready to process the next input signal.

When errors are detected in combination A, it is fed through the second element OR 19 to the input of register 7, where it is stored, and to the first input of decoder 4, which is identified with the nearest allowed code combination A. After writing to the register 7 of all H binary signals corresponding to the symbols of the combination A, in the decoder 4 binary code combinations are formed corresponding to the most jBepoHTHbiN: error vectors, which

a single signal appears at the output of the decoder, connected not only to the corresponding input of register 26, but also to generator 27, and trigger 2-1,

This single signal stops the generator 27 and changes the state of the flip-flop 21, as a result of which the key 20 closes. After that, the output of the second shaper 28 pulses gives rise to read pulses from the registers 7 (already without regeneration), 26 and 9. At the same time, the output binary signals of the modulo-10 adder are written to the first register 9 of the register block 8. Upon completion of the read pulses, a binary code pattern A is recorded in the first register 9, which differs from the initial combination of register 7 (at this time it is read from register 7) in the last bit,

and in the last register (9.,) -. . ., h

Nation A differs from the original combination of register 7 in the first discharge.

Next, from block 8 of the registers, the combinations read .. and process. The algorithm of this processing will consider the example of processing a combination of A,

Binary code combination A from the output of block 8 of registers is fed to decoder -12, which detects errors. In decoder 12, pattern A is analyzed for errors. If there are none, then this combination through the OR element 13 returns to the output of the device, after which all the blocks are reset and the processing cycle of the next composite signal begins.

If errors exist in A, then this combination is sent to the decode p 4, which corrects errors. In decoder 4, combination A. is identified with the nearest allowed binary code combination A. This allowed combination is written into block 5 of registers. In this case, the analyzer 14 does not perceive the allowed combination

The rest of the combinations read from the register block 8 are processed in a similar way, as a result of which in the register block 5 there will be also recorded H-1 allowed combinations, so that their total number in this block is equal to H plus one.

2332016

Then, an accurate estimate of the X composite signal with redundancy comes from the memory block 2 to the control signal generator 6, and the binary allowed code combinations are read from the block 5 5. In shaper 6, which of all the allowed-code combinations is determined most closely to the signal

10 accurate estimates of X (most correlated with X). This combination is read by the control signal from the driver b in block 5 from the last step a. device output through

15 element OR 13. After that, all the blocks of the device are reset, and the device is ready to process the next composite signal with redundancy.

20 The technical advantage of the proposed device is the formation of not one, but a combination of the most probable error vectors in the case where the vector estimate

 the error corresponds to the multiplicity of the most correctable error.

The positive effect is to improve the noise immunity of receiving redundant signals.

30 Approximate gain: with regard to noise immunity, the reception of a composite signal with redundancy can be determined as follows.

The accuracy of correct reception of a composite signal with redundancy — using a known device can be determined as:

t-1

, H-1

p z: c p (i-p) + K cVci-p),

i - o. .

0 (1)

where K - coefficient taking into account

the effect of failures (for example, in decoder 4, which corrects errors.) with an error vector weight equal to T.

The accuracy of correct reception of a composite signal with redundancy using the proposed device can be defined as: 0 Т-1; . nt nt

РЗ Е: С; Р (ь) + к) (2) From comparison of expressions (1) and (2)

follows that

5p p

 TO

those. The present invention has a higher noise immunity compared with the known.

otlnchy of areas of elimination of the symbolic and reception as a whole. Combination A is recorded in block 5 of the registers and in register 16 of the analyzer 14. In the analyzer 14

Hammin-govo distance calculated

R

between combinations A and A. If this distance is less than the multiplicity T of the error code to be corrected, then A is output from the analyzer 14 through the element OR 13 to the device output., The generation of binary code combinations is stopped, all the blocks are reset to the initial state and the device is ready for processing the next signal .

R

Otherwise (A is not remote from A by a distance less than T), the formation of binary code combinations, which is next.

After all the memory cells of register 7 are filled with the corresponding binary signals (symbols), a control signal is generated at the output of the element 22, which starts the generator 27 clock pulses. At the output of the generator 27, clock pulses are generated at the corresponding points in time, ((

Let the first clock pulse be formed at the output of generator 27.

This pulse is applied to the first input of the pulse driver 23 and through the delay element 32 to the input of the second pulse driver 28.

In the pulse former 23, the first pulse is fed to the input of the counter 24, and changes its state. The new state of the counter 24 in the form of a corresponding parallel binary code is fed to the inputs of the decoder 25, which converts the parallel binary code of the state of the counter 24 into the output parallel positional binary code. Thus, the decoder 25 converts the binary code of the number of the output pulse of the generator 27 into a binary output signal, which is generated at the output of the decoder 25 (this double signal is single) with the same number, which is the number of the output pulse of the generator 27. Therefore In this case, a binary signal 1 is generated at the first output of the decoder 25. In this case, it is possible to indicate that at the output

332014

A decoder 25 forms a parallel H-valued binary code combination with unit weight. This binary code combination is written 5 n register 26.

From the output of the delay element 32, the first output pulse of the generator 27 is fed to the input of the trigger 30 of the second driver 28 of the pulses. The trigger 10 of the transmitter 30 changes its state:

its output signal appears, the trigger generator 29 clock pulses with output, the generator pulses 29 are fed to the output of the driver 28 and

5, the input of the counter 31 (an overflow pulse at the output of the counter 31 appears when an H - pulse arrives at its input). After the generator 29 generates H clock pulses, the output of the counter 31 results in an overflow pulse, which returns the trigger 30 to its initial state. When this generator 29 stops the formation of pulses.

25

The output clock of the second

shaper 28 is fed to the control inputs of the registers 7.26 9 (total registers 9 N pieces). At the same time, the output signals of register 7 through the open state of the key 20 and the element OR 19 are rewritten into the same register 7 and are also fed to the nepBfjm input of the adder 10 per m / n. Two. The second input of the adder 10 is sequentially inputted. register 26. The output signals of the adder 10 write € 1 ms to the first register of block 8 registers. Obviously, using the adder 10 for g / I am two

thirty

40

the binary signal of the register 7j is inverted, the sequence number of which coincides with the order of the single signal in register 26.

 Next, the generator 27 generates subsequent clock pulses, and the corresponding binary combinations are written to the registers 9, successively moving forward.

SO Let the last pulse be generated at the generator 27 output. This pulse converts the counter 24 to the state K, the binary code of which with the help of the decoder 25 pre-55 is formed into the position code of unit weight, which is written in the register as a BOLUTH diany unit weight. 26, With this

The advantage of the invention is the more significant, the more powerful the error-correcting code (i.e., more

N and t) and above the quality of the communication channel. one

Claims (3)

1. A device for receiving and processing redundant signals comprising a demodulator whose input is an input of a device, an output of a demodulator is connected via a memory unit to a first input of a control signal generator and an input of a threshold element, the output of a threshold element is connected to the input of a first decoder, the first output of which is connected to the first input of the first OR element, the second output is connected to the first input of the second decoder, the output of the second decoder is connected to the first inputs of the analyzer and the first block of registers, the first The one and second inputs of the first block of registers are connected respectively to the second input and output of the control signal generator, the second input of the first block of registers and the analyzer output are connected to the second and third inputs of the first OR element, the fourth input of which is connected to the first output of the third decoder, respectively. the first element OR is the output of the device, the register, the first outputs of which are connected to the corresponding second inputs of the analyzer, the second output of the register is connected to the first input of the adder, the second The adder's input is connected to the first output of the first pulse generator, so that, in order to improve the noise immunity of the device, a second block is inserted into it. Registrar the second pulse shaper, trigger, key, And element, the second element OR, the delay element and the clock pulse generator, the inputs of the AND element are connected to the corresponding first register inputs, the output of the AND element is connected to the first input of the clock pulse generator, the output of which is connected directly to the PNRI. Order 2775/53 Circulation 515 Random polygons pr-tie, Uzhgorod, st. Project, 4 0 five 0 The 5th input of the first pulse generator and through the delay element to the left input of the second driver, 1 pulse, the output of the first pulse generator is connected directly to the second input of the clock generator and through the trigger to the control input of the key, the information input of which is connected to the second output register, the key output is connected to the first input of the second OR element, the second input of which is connected to the second output of the first decoder, the output of the second OR element is connected to the information input of the register, the output of the second pulse shaper is connected to the second input of the first pulse shaper and the control inputs of the register and the second register block, the output of the adder is connected to the information input of the second register block whose output is connected to the third decoder input, the second output of which is connected to the second input of the second decoder. with 2. The device according to claim 1, which differs from the fact that the first pulse shaper contains a counter, a decoder and a register, the outputs of the counter are connected to the corresponding inputs of the decoder, the first and second codes of which are connected, respectively, to the first and second information the inputs of the register, the input of the counter and the control input of the register are the first and second inputs of the first pulse shaper, the output of the register is the output of the first pulse shaper. 3. The device according to claim 1, that is, that the second impulse generator contains a counter, a trigger and a generator of clock pulses, the output of the counter is connected to the first trigger input, the trigger output is connected via a clock generator to the counter input, the second trigger input and the clock generator output are respectively the input and output of the second pulse generator. Subscription