SU1229792A1 - Device for transmission and reception of digital signals - Google Patents

Abstract

The invention relates to automation and computer technology and can be used to transmit and receive digital signals from automated test control systems of the UTC type to the monitored digital module up to 2.5 m. The accuracy of the device is improved by providing automatic transmission channel switching and receiving digital signals. It is possible to control the passage of signals. By introducing the trigger 19 into the device, the comparison circuit 20, the elements Y-NOT 22, W-NOT 21, NOT 1, 4, 3, it is possible to automate the switching of channels on the transmission from one object to another and back. The insertion of the LED 23 allows control of the signal flow. 3 il. (L U "H f. L." gd; ND N9; about with to

Description

one

The invention relates to automation and computer technology and can be used to transmit and receive digital signals from automated TTC-type automated test control installations to a monitored digital module up to 2.5 m.

The purpose of the invention is to increase the accuracy of the device when transmitting and receiving digital signals by providing automatic switching of the channel for transmitting and receiving digital signals, as well as the ability to control the passage of signals.

Fig; 1 shows the scheme of the proposed device; FIG. 2 are time diagrams; there is a logical level on the pin of the UTK channel connector; in fig. 3- the same, on the connector pin of the channel UTK there is a high logic level.

The device contains (Fig. 1) elements NOT 1-4, data buses 5 and 6, resistors 7-15, buttons 16 and 17,

pulse shaper 18, trigger 19, reference element 20, W-NE 21 element, N-NE element 22, LED 23, first 24 and second 25 power buses.

The device works as follows.

When the button 17 is pressed, a potential zero arrives at the input of the zero setting of the flip-flop 19 and a low logic level is set at the trigger output. Let-on the pin of the UTK channel connector there is a low logic level (Fig. 2). When the button 16 is pressed, the pulse shaper 18 generates a pulse, which is fed to the trigger synchronization input, since a low logic level is present at the trigger information recording input, then the logic zero level will remain at the trigger output.

From the trigger output 19, the low logic level goes to the second inputs of the comparison element 20 and the NAND element 22, as well as the input of the NOT 4 element. Despite the fact that there is a low logic level at the second input of the NAND 22 element, its output there is not a high logic level, no matter what signal arrives at its per 297922

the left input, and a low one, since the open transistor of the UTK channel shunts the closed output transistor of the NAND element 22. At the combined outputs

5 elements of NOT 1 and element 4 is set to a high logic level, as their inputs receive low logic levels. NOT 1 high boolean output

 About the level through the bus 6 data to the input element NO 2, the output of which is set low logic level. At the exit of the element NO 3 is set accordingly high.

15 logic level, which through the bus 5 data is fed to the first inputs of the elements SHI-NOT 21 and AND-NOT 22.

The inputs of the element OR NOT 2G receive high logic levels,

20 therefore, at its output a low logic level, which goes to the second input of the comparison element 18, since the signal levels at the circuit inputs are equal, then its output will be

25 high level and LED 2 is off. Thus, the test signals from the output of the UTK channel are transmitted via the NOT I element, the data bus 4 and the NOT 2 element to the input of the counterpart digital module. If there is a high logic level on the pin connector of the UTK channel (Fig. 3), then after recording this signal at the output of the trigger 19 there is a high logic level that goes to the input of the HE element 4. A low logic level is set at its output, which goes through the bus 4 entry data

 NOT 2, the output of the latter is set to a high logic level. At the output of the element NO 3 there is a low logic level that goes to the first inputs of the element.

 IPI-NO 21 and the element AND-NO 22. At the outputs of the elements AND-NO 22 and the IPI-NO 21 there are high logic levels.

At the output of the comparison circuit 18, there is a high logic level and

 LED 23 is off. Thus, the output signals from the monitored module are transmitted through the NOT 3 element, the data bus 5, and the NAND element 22 to the input of the TC channel.

55 When transmitting digital test signals (low frequency), regardless of the direction of signal transmission, the LED does not operate in a blinking mode.

3

and thus, the health of the channel of the device is monitored.

Claims (1)

Invention Formula A device for transmitting and receiving digital signals containing resistors, the first terminals of the first and second resistors are connected to the primary power bus, the first element, whose output is connected to the second terminal of the first resistor, is required in order to improve the accuracy devices and expanding the functionality by controlling the passage of signals, elements are NOT, NONE, OR NONE, resistors, LED, trigger, comparison element, pulse shaper, button and second power bus, the second you the water of the first and second resistors are respectively the inputs and outputs of the device, the first terminals of the third, fourth, fifth and sixth resistors are connected to the first power bus, the first terminals of the seventh and eighth resistors are connected to fig 2 0 29792 4 The second power bus, the second outputs of the fourth, sixth and seventh resistors are connected to the input of the first element NOT, whose output through the second 5 element is NOT connected to the first inputs of the AND-NOT, OR-NOT elements and the second terminals of the third, fifth and eighth resistors, output element is NOT connected to the second output of the second resistor, the trigger recording input and through the third element NOT to the input of the first element NOT and the second input of the element OR NOT whose output is sub-key to the first input of the element 5 comparison, the output of which is connected to the first power bus through the ninth resistor and LED, the first outlets of the first and second buttons are connected to the second power bus, the second output of the first button is connected to the trigger input, the output of which is connected to the second input of the comparison element, the second input of the element AND- NOT and through the fourth element NOT - with 5 second step of the sixth resistor the second second of the second button through the pulse shaper is connected to the trigger synchronization input. fig.Z