SU1228055A1 - Probe for testing signals of digital microcircuits - Google Patents

Abstract

The invention relates to a pulse technique, can be used in setting up and checking the health of semiconductor digital devices with three stable states. The purpose of the invention is to expand the scope of application to the functionality, achieved by reducing the potential on the probe, not exceeding the supply voltage of the monitored circuits, and allowing the recording of a signal corresponding to the signal of the free input of microcircuits. The device contains a switch I, resistors 2, 4, 6, 14, 15 and 17, a logic converter 7, an indicator 8, transistors 3, 5, 9, II and 16, a probe 10, adjustable sources of reference voltage 12 and 13. The device allows It does not distinguish the input of the logic element from the output in the high-impedance state. Eliminates on the probe 10 a potential greater than the supply voltage level. I il. (L yu (O 00 about ate

Description

The invention relates to a pulse technique and can be used in setting up and checking the health of semiconductor digital devices with three stable states.

The purpose of the invention is to expand the field of application by reducing the potential on the probe, not exceeding the supply voltage of controlled circuits and expanding the functionality as a result of enabling the recording of a signal corresponding to its free chip input signal.

The drawing shows a block diagram of a probe for checking digital microcircuit signals.

The probe for checking digital microcircuit signals contains a key 1, the first output of which is connected to the first output of the first resistor 2, and the second output is directly connected to the collector of the first transistor 3 and connected via the second resistor 4 to the base of the second transistor 5, emitter connected to the common bus, the third resistor 6 to the power bar and directly to the first input of the logic converter 7, the output of which is connected to the input of the indicator 8, and the second input is connected to the collector of the third transistor 9, the emitter of which is One with the emitter of the first transistor 3, the probe U and the emitter of the fourth transistor 11, while the bases of the first and third transistors 3 and 9 are connected to the output of the first adjustable source 12 of the reference voltage, and the output of the second adjustable source 13 of the reference voltage is connected to the base of the fourth transistor 11, the collector of the zero potential connected via the fourth resistor 14 and the fifth resistor 15 to the base of the fifth transistor 16, the emitter is connected to the common bus, and the collector is connected via the sixth resistor 17 to the bus power supply (E) and directly to the second input of the logic converter 7.

The device works as follows.

The source 12 of the reference voltage is regulated so that the transistor 9 is open when the voltage on the probe 10 does not exceed the upper value "O. The source 13 of the reference voltage is adjusted so that the transistor 11 is opened only when the voltage on the probe 10 exceeds the lower value "1.

On the probe 10 served "O. Key 1 is closed. The transistors 11 and 3 are closed and the transistors 16 and 5 are kept in the closed state. The closed transistor 5 supplies "1 to the first input of the logic converter 7." O on the probe 10 and the emitter of the transistor 9 opens the transistor 9, which despite the closed transistor 16 creates " On the second input of the logic converter 7. Thus, on the first and second inputs of the logic converter 7, there is the code "10, which is decrypted by the logic converter 7 and visualized by the indicator 8 as" O.

On probe 10 is filed «1. Key 1 is closed. The transistor 9 is closed by a high potential "1 on the emitter. Transistors 11 and 3 are open and transistors 16 and 5 are opened by a collector current. Open transistor 5

creates an “O” at the first input of the logic converter 7. The open transistor 16 despite the closed transistor 9 provides “O at the second input of the logic converter 7. Thus, when“ 1 ”on the probe 10, the code“ 00 ”is decrypted by the logical the transducer 7 and is visualized by the indicator 8 as

five

The probe 10 is supplied with an intermediate level between “O” and “1 signal level from a low-impedance source. Key 1 is closed. The signal on the probe 10, which exceeds the level “O opens transistor 3 and the collector current opens transistor 5, which creates“ O on the first input of the logic converter

5 7. Transistors 11 and 9 are closed and together provide “1” at the second input. Thus, at the inputs of the logic converter there is a code "01, which is deciphered by the logic converter 7 and visualized by the indicator 8 as an intermediate between" O and "1.

The probe 10 is connected to the output in a high impedance state (or break). Key 1 is closed. The high-resistance output of a logic element, although it has a potential in a free state, is intermediate between "O and" 1, but does not have a load capacity, i.e., when connected to a resistor 2, it is not enough for the transistor 5 to have a base-emitter current to open the transistor 5. Transistor 5 is closed,

Q which causes "1 at the first input of block 7. Transistors 11 and 9 are also closed, since there is no base-emitter current, and therefore they create" 1 at the second input of block 7. Thus, when key 1 is closed and high-impedance state is on dipstick 10

5 at the inputs of block 7 there is a code "11, which is recognized as a high-impedance state.

The high impedance output of a logic element can be an input element or an output that is in a high-impedance state.

The high impedance output of a logic element can be an input element or an output that is in a high impedance state. The input current of the logic element is by J order greater than the short-circuit current of an output that is in a high-impedance state. This property allows us to distinguish an input from an output in a high-impedance state. Opening the key 1 eliminates the shunting effect of the resistor 2 and the input current of the checked logic element through the probe 10, the transistor 3 through the base-emitter circuit of the transistor 5 opens the transistor 5, which causes "O on the first input of the block 7. The output current in the high impedance state is not enough to open the transistor 5 along the same circuit, and the transistor 5 remains closed, at the first input of the block 7 "1 does not change.

Thus, when the key is closed, 1 at the inputs of the logic converter 7, depending on the signal on the probe 10, there are codes: logical zero - 10; logical unit - 00; intermediate level between “О and“ 1 - 01; high impedance state - 11.

After a high-impedance state is detected by opening the key 1, the input of the logic element is distinguished from the output in the high-impedance state. The code "01 at the inputs of block 7 corresponds to the input of the logic element, and the code" 11 to the output in a high impedance state.

The remaining elements of the device have the following purpose.

connected to the collector of the third transistor; Resistors 4 and 15 provide a working torus 25, the emitter of which is connected to the probe.

the mode of transistors 5 and 16. Resistor 14 serves as a load for a logic element at level “1. Resistors 6 and 17 are the load of transistors 5 and 16.

Thus, the logic converter can be implemented using a read-only memory (ROM) format that provides storage of four seven-bit words. A seven-segment LED indicator can be used as an indicator.

The proposed device allows to distinguish the input of the logic element from the output in the high-impedance state and exclude

thirty

35

and the base of the third transistor is connected to the output of the first adjustable voltage source and to the base of the first transistor, the emitter of which is connected to the probe and emitter of the fourth transistor, the base of which is connected to the output of the second adjustable voltage source, the fourth transistor is connected to the common transistor bus and through the fifth resistor with the base of the fifth transistor, the emitter of which is connected to the common bus, the collector is connected through the sixth resistor to the power bus and directly on a second input of the logic inverter.

0

on the probe potential greater than the supply voltage level.

Claims (1)

Invention Formula A probe for checking digital microcircuit signals containing two adjustable reference voltage sources, a probe and a logic converter, the output of which is connected to an indicator, characterized in that in order to expand the field of application by reducing the potential on the probe and extending the functionality as a result of the possibility of recording the signal corresponding to the free chip input signal, entered into it are resistors, five transistors and a key connected by the first pin through the first cut Torr to a common bus, a second terminal directly connected with the collector of the first transistor, and through a second resistor coupled to the base of the second transistor, the emitter of which is connected to the common bus, a collector through a third resistor connected to the power bus and directly to a first input of a logic converter, the second input of which five 0 five and the base of the third transistor is connected to the output of the first adjustable voltage source and to the base of the first transistor, the emitter of which is connected to the probe and emitter of the fourth transistor, the base of which is connected to the output of the second adjustable voltage source, the fourth transistor is connected to the common transistor bus and through the fifth resistor with the base of the fifth transistor, the emitter of which is connected to the common bus, the collector is connected through the sixth resistor to the power bus and directly on a second input of the logic inverter.