SU1226643A1 - Connector of multistage switching system - Google Patents

Abstract

The invention relates to an impulse technology, electronic switching and communication and can be used in computational and automatic systems with a tunable structure. The purpose of the invention is to increase the speed, reliability of operation and expansion of functionality. Connector 1 contains a matrix switch 2, a channel blocking unit 5, connection fixation matrices 7, an address switch 9, an address control block 12, an address decryption block 13, an acknowledgment sending block 14, a confirmation receiving block 16, a priority block 17, a block 18 synchronization, block 21 for exiting outputs, block 22 for fixing requests, a group of information inputs and a group of information outputs. Introduction to the device of the matrix switch of addresses, blocks of tracting addresses, their decoding, sending and receiving confirmation, priority, synchronization, occupancy of outputs, fixation of requests made it possible to ensure single parallel search and fixation of an arbitrary number of channels in a multi-stage switching system. 15 il. WITH

Description

The invention relates to a pulsed electronic switching and communication technology and can be used in computing and automatic systems with a tunable structure.

The purpose of the invention is to increase the speed, reliability of operation and enhancement of functionality due to the simultaneous parallel search and fixation of an arbitrary number of channels in a multi-stage switching system.

FIG. 1 shows the block diagram of the multi-stage switching system connector (,,,); in fig. 2 - functional scheme of the // fixation unit; in fig. 3 - the organization of communications of the fixation units of the compounds in the matrix of the fixation of the compounds; in fig. 4 shows functional diagrams of drivers and acknowledgment receivers and their connection as part of the sending and receiving block of confirmation; in fig. 5 is a functional block diagram of address decoding; in fig. 6 is a functional diagram of the request fixing node and its communication as part of the request fixing block; in fig. 7 is a functional diagram of an output occupancy node and its communication as part of an output occupancy unit; in fig. 8 is a functional block of the priority block with the priority function “less than the sequence number of the input — the priority is higher and its connections are within the priority block; in fig. 9 is a functional diagram of a matrix address switch; in fig. 10 is a functional diagram of an address management node; in fig. And - the organization of communications of the address control nodes in the address control block; in fig. 12 shows functional diagrams of a switching node and a channel controlling node and their communication; in fig. 3 is a functional diagram of a single-ended synchronization unit; in fig. 14 is a simplified configuration block diagram of a multi-stage switching system in which,,, FIG. 15 is a three-stage switching system constructed from these electronic connectors.

Connector 1 of a multi-stage switching system (Fig. 1) contains a matrix switch 2, a group of t information inputs 3 of a matrix switch 2, is a ush, a usy group of information inputs 20

The TOGO contains a matrix switch 9 addresses, a group of address inputs 10 of a nickname address switch, a group of address inputs of connector 1, a group of address outputs 11 of a matrix switch 9 addresses, a group of address outputs of connector I, an address control block 12 , address decryption unit 13, confirmation confirmation block 14, the mode input 15 of which is the input

10 of connector mode 1, confirmation receipt block 16, priority block 17, synchronization block 18, setting input 19, and a group of clock inputs 20 of which are a setting input and a group of clock inputs of connector 1, respectively, block 21

15 occupancy of outputs, block 22 of request locking, a group of inputs of which is connected to the second outputs 23 of matrix 7 of connection fixation. The first group of inputs 24 of the connection fixing matrix 7 is connected to the output group of the priority unit 7, the input group of which is connected to the input group of the output occupancy block 21 and the third group of outputs 25 of the connection fixation matrix 7, the second input group 26 of which is connected to the first output group of the block 21 occupancy of outputs, the second group of outputs 27 of which is connected to the group of inputs of block 14 of the confirmation send, group of outputs 28 of which is connected to group of outputs 11 of a matrix switch 9 of addresses, group of inputs 10 of which dinene with a group of inputs 29 of the confirmation receiving unit 16, the output group of which is connected to the third group of inputs 30 of the connection fixation matrix 7, the fourth group of inputs 31 of which is connected to the output group of the address decryption unit 13, the input group of which is connected to the input group of the matrix 9 address switch, the control input group of which is connected to the output group 32 of the address control unit 12, the first group

Q inputs 33 of which is connected to a group of outputs 6 of the connection fixing matrix 7, and the second group of inputs 34 of the address control unit 12 is connected to the first group of outputs of the request fixing block 22, the second group of outputs of which is connected to the fourth group of inputs 35 of the connection fixing matrix 7, the first the control input 36 is connected to the first output of the synchronization unit 18, the second output 37 of which is connected to the second control input of the connection fixation matrix 7.

25

35

Connector 1, a group of n information is the first control input of the receiving unit 16

matrix outputs 2, the group of information outputs of connector 1, the channel control block 5, the outputs of which are connected to the control inputs of the matrix switch 2, and the inputs to the group of outputs 6 of the connection fixing matrix 7, to connect the switch . Electronic connector 1, except

confirmation by the first control input unit 14 of the confirmation send, the first control input of the address control unit 12, the second control input of which is connected to the control input of the channel control control unit 5, 1 network output 38 of the synchronization unit 18, the fourth output 39 of which is connected to the first input control unit 21 occupancy of outputs, the third

0

The TOGO contains a matrix switch 9 addresses, a group of address inputs 10 of a nickname address switch, a group of address inputs of connector 1, a group of address outputs 11 of a matrix switch 9 addresses, a group of address outputs of connector I, an address control block 12 , address decryption unit 13, confirmation confirmation block 14, the mode input 15 of which is the input

0 of connector mode 1, confirmation receipt block 16, priority block 17, synchronization block 18, setup input 19, and clock input group 20 of which are the tuning input and clock input group of connector 1, respectively, block 21

5 outputs, a request fixation block 22, a group of inputs of which is connected to the second outputs 23 of the connection fixation matrix 7. The first group of inputs 24 of the connection fixing matrix 7 is connected to the output group of the priority unit 7, the input group of which is connected to the input group of the output occupancy block 21 and the third group of outputs 25 of the connection fixation matrix 7, the second input group 26 of which is connected to the first output group of the block 21 of the outputs, the second group of outputs 27 of which is connected to the group of inputs of the confirmation sending unit 14, the group of outputs 28 of which is connected to the group of outputs 11 of the matrix switch 9 of addresses, the group of inputs 10 of which inen with a group of inputs 29 of the confirmation reception block 16, the output group of which is connected to the third group of inputs 30 of the connection fixing matrix 7, the fourth group of inputs 31 of which is connected to the output group of the address decryption unit 13, the input group of which is connected to the input group of the matrix 9 address switch, the control input group of which is connected to the output group 32 of the address control unit 12, the first group

Q inputs 33 of which is connected to a group of outputs 6 of the connection fixing matrix 7, and the second group of inputs 34 of the address control unit 12 is connected to the first group of outputs of the request fixing block 22, the second group of outputs of which is connected to the fourth group of inputs 35 of the connection fixing matrix 7, the first the control input 36 is connected to the first output of the synchronization unit 18, the second output 37 of which is connected to the second control input of the connection fixation matrix 7.

five

five

0 the first control input of the receiving unit 16

confirmation by the first control input unit 14 of the confirmation send, the first control input of the address control unit 12, the second control input of which is connected to the control input of the channel control control unit 5, 1 network output 38 of the synchronization unit 18, the fourth output 39 of which is connected to the first input control unit 21 occupancy of outputs, the third

the control input of the connection fixation matrix 7, the first control input of the request fixing unit 22, the second control input of which is connected to the second control input of the confirmation receiving unit 16, the fifth output 40 of the synchronization unit 18, the fourth control input of the connection fixation matrix 7 connected to the sixth output 41 of the synchronization unit 18, the seventh output 42 of which is connected to the third control input of the confirmation receiving unit 16, with the second control input of the confirmation sending unit 14. The functional diagram (Fig. 2) of the node 43 g / connection fixation, which is an element of the connection fixation matrix 7, contains a trigger 44, logic gates AND 45-48, and a logic element OR 49. Connection organization of the 43m-43t nodes to fix connections in connection fixation matrix 7 is shown in FIG. 3. The functional diagrams of the driver 50 of confirmation and organization of connections 50 | -50 "within the block 14 of the confirmation confirmation can be performed in two versions (Fig. 4). In the first embodiment, the circuit contains an amplifier 51 with three stable states, the input 52 of which mode is connected to the element 53. The confirmation driver 50-2, made according to the second variant and containing the element 54, is expedient to apply in cases where logical unit corresponds to low voltage level. The functional diagram of the confirmation receiver 55 and the organization of the connections 55i-55 ,,, as part of the confirmation reception unit 16 (Fig. 4), contains a trigger 56 and an And 57 element. The address decoding unit 13 consists of t decoders 58 (Fig. 5). The links of the decoders 58i - 58 ', as part of the address decoding unit 13, are shown in FIG. 5. The functional diagram (Fig. 6) of the request fixing node 59 contains a trigger 60, an AND 61 element and an OR 62 element. 6. A functional diagram of the output occupancy node 63 (FIG. 7) contains a trigger 64, an AND element 65, and an OR element 66. The connections of the 63i-63, node occupancy of the outputs in the output occupancy unit 21 are shown in FIG. 7. The functional diagram of the arbiter 67 / -line (FIG. 8), which is an element of the priority block 17, contains (for the case of the priority block with priority latching, “the order number of the input is higher than the priority) the logical zero and w - 1 generator 68 elements OR 69 with a different number of inputs. FIG. 8 shows a functional diagram of a priority block 17 consisting of n arbitrators. The functional diagram of the matrix switch 9 addresses (Fig. 9), built on the switching elements for one input and one output, for switching groups of inputs 10, where each input consists of k physical lines, into a group of n outputs 11, where each output consists of k physical lines. The circuit contains mXnXk switching elements 70. The address control unit 71, / (addressing FIG. 10) is an element of the address control block 12. The organization of communications between nodes 71 and 71 - 71, inside the address control block 12 is shown in FIG. P. Node 71 ,, (FIG. 10) consists of AND 72 and 73 elements, OR element 74, and level matching element 75.

The matrix switch 2 channels (Fig. 12) differs from the matrix switch 9 addresses (Fig. 9) by the number of physical lines in one input or output. In the matrix commutator there are 2 channels of d physical lines. Node 76; The switching points (-c1in, / -input on / -output (Fig. 12) consists of 77g / switching elements. The total number of .10 switching nodes 76 is equal. Each switching node 76 is controlled by a channel control node 78, which is an element of the 5 channel control. Each of the tX "control nodes 78 consists of an element AND 79 and an element 80 matching

5 levels. An important difference between a 2-channel switch and an 9-address switch is that it can switch both discrete and analog signals. A 2 channel switch can be made using keys from any physical

From gfirody (klyu1 (and on bipolar, unipolar and four-layer devices, / 7 - / - p-prbbor, opto-electronic keys, reed and eromagnetic relays, ferrides, etc.).

Single-ended clock input pulses

5 to 20 (Fig. 13) are converted to three-stroke in synchronization unit 18, in which the node 81 for converting the phases, consisting of elements 82 and 83 of pulse delays, converts the input sequence of pulses into a three-stroke sequence. And the pulse at exit 39 appears after the end of the pulse at input 36, the pulse at exit 42 after the end of the pulse at output 39, and the pulse at input 36 after the end of the pulse at output 42 and

5 for a pause, then a pulse appears at the output 39, etc. The synchronization node 84 of the synchronization unit 18 is executed on triggers 85-87, logic gates AND 88-91, logic gates And 92 - 94. The state changes at the outputs 37 ,

0 38, 41 and 40 can occur only in the pause between the end of the signal at the output 42 and the appearance of the signal at the output 36. The circuit of the synchronization unit 18 (FIG. 13) can be easily converted to three-stroke if the three-stroke input pulses are directly supplied from the clock inputs 20 to input 36 and outputs 39 and 42. Block 18 С11Нх) isolation can be performed both in a push-pull and four-stroke 11 scheme.

five

The device works as follows.

When establishing connections, the input priority is 10 | above the entrance of yua. For normal operation of the device, clock pulses must be continuously applied to input 20. In the "Information transfer" mode (logical zero at input 19), the output 37 of all connections fixing nodes 43 (Fig. 2) is given a logical zero, which prevents the matrix switches 2 and 9 from changing by an arbitrary combination of signals at the inputs Yun , lOiz, lOai, 1022 and 15. In the mode of establishing connections (logical unit at input 19), output address codes are sent to address inputs 101 and 102. Consider the case when the logical “1” arrives at the input of lOii, and the logical “O. When a strobe signal appears (logical "1 at 10: 2 input) at input 3112 (Fig. 5), logical" 1 appears. When a strobe signal appears at input 1022, the logical "1 at input 3l2i appears. If the logical "1 at the input of the element P 46 and the logical" 1 coincides at the inputs 26 of the element And 47, the corresponding trigger 44 is turned on (Fig. 2). For this case, a strobe signal at input 10i2 translates into one state the trigger 44 of node 43 | 2 of connection fixation, and the gate at input 1022 - trigger 44 of node 432i of connection fixation (Fig. 3). Switching of the flip-flops 44 to a single state occurs only at the moment of the arrival of the first internal clock pulse (TI 1) from the input 36 of the synchronization unit 18 (FIGS. 2 and 13). The second internal clocking pulse (TP 2) from the output 39 of the synchronization unit 18 converts the triggers 60 nodes into a single state 59 | n 592 requests fixing (Fig. 6) and triggers 64 nodes 63) and 632 occupancy of outputs (Fig. 7), which leads to the appearance of logical "O at inputs 35 |, 352, 26, and 2b2 (Fig. 3) . Triggers 44 nodes 43 | and 4322 fixing of connections could not be accomplished before resetting to the zero state of the flip-flop 60 of the nodes 59i and 592 of fixing requests and flip-flops of the 64 of the 63i and 632 occupation of the outputs (Fig. 2-3). TI 2 strobes the reset of trigger 44, which enters the circuit of elements 48 and 48, or 49 (Fig. 2). In this case, the inputs 24c and 24c are logical 0, since they are connected to the outputs of the formers 68 logical zero, at input 24i2 logical "O, since the input element OR signal is equal to logical" O, at input 2422 a logical unit (Fig. 2 -eight). Consequently, a reset signal is sent to the R-input of trigger 44 of node 4322. But since this trigger is in the zero state, the reset signal does not affect the state of the connection fixation matrix 7. In the case of a request to connect with one output from several inputs 10 per line

d

the fixation matrices 7 corresponding to this output 11, in cycle TI 1, the triggers 44 of the corresponding inputs 10 are translated into one state. In cycle TI 2, the triggers corresponding to the inputs with b priority are reset to the “zero state. Thus, at the end of the TI 2 clock cycle, in each row of the connection fixation matrix 7, the state of the logical unit is not more than one trigger). The third internal clock pulse (TI 3) from the output 42 of the synchronization unit 18 is used to fix the connecting path. If the connector 1 of the multi-stage switching system (Fig. 14) is located in the latter (when transmitting the address information from left to right in the rightmost one), then the logical input is fed to the input 15 of the mode. Before the arrival of TI 3, address links in the matrix switch 9 of addresses must be connected (Fig. 9). In this case, the elements 70i2i are included. 70i22: 70211. 70212 switching, where the left index bit is the input number, the average index bit is the output number, and the right index bit is the number of the address bit. Accordingly, a logical unit is present at the outputs 32 | 2 and control switching elements 70.

The control signal (Fig. 10) for switching on the switching elements 70 arrives not earlier than the occurrence of the signal at the inputs 34i

0 and 342 (Fig. 11), plus the response delay of the AND 72, OR 74 elements and, in the general case, the level matching element 75. In turn, the signals at the inputs 34 and 342 of the node 59i and 592 of the fixation of requests are reliable since the appearance of TI 2

5 (input 39) plus the response delays of the elements OR 62, AND 61 and trigger 60 (FIG. 6). If at input 15 (FIG. 4) of the logical mode "1 and the connector 1 is in the tuning mode (logical 1 at the output 38 of the synchronization unit 18), then by the TI 3 signal a confirmation signal from the outputs 28 and 282 of the drivers 50 | and 502 arrives at outputs 11: and 1b of the matrix switch 9 of addresses (in Fig. 14 there are conditionally shown connecting the group of inputs 10 and output groups 1 1 for a given connection program). The signal from the output 28 of the confirmation block 14 is sent to the input 292 of the confirmation receiving block 16, and from the output 282 to the input 29 :. Confirmation reception unit 16 is gated by TI 3. Triggers 56 of receivers 55: and 552 confirmations of confirmation block 16 are cocked into one state (Fig. 4). Confirmation signals to the Ili2 and 1022, N22 and 10: 2 teams are received on the previous 11 lines.

5 cascade switching system. After completing the settings. And to the input 19, the settings are given a logical zero, which corresponds to the mode of information transfer through

connector 1. At the time of the mode change, a single pulse is produced at the output 41 of the synchronization unit 18 (FIG. 3), which flushes the triggers 44 of the connection fixation nodes 43 (FIG. 2) to the zero state, which are not received. the signal at input 30. From the output of those triggers, the reset of which to the zero state is blocked (in this example, the triggers of 44 nodes 4312 and connection fixation) from the confirmation receiving unit 16, the logical unit is fed to the inputs of the channel control unit 5. In the information transfer mode, the output 38 of the block 18 is a logical unit (Fig. 12). For a given connection program, the logical unit at the outputs 6i2 and 621 (Fig. 12) and, accordingly, the elements 77, are included. , 77 "d and 77218 co-mutations (in Fig. 14, the circles conditionally show the connection in the matrix switch of 2 channels of a group of inputs 3 and a group of outputs 4). When switching from the information transfer mode to the setting mode (a logical unit is fed to the input 19 of the connector 1 instead of a logical zero) the output 40 of the synchronization unit 18 (Fig. 13) produces a single impulse (Fig. 2), which resets the triggers 44 matrix 7 fixation of compounds. FIG. 15 shows a three-stage switching system having eight inputs and eight outputs for transmitting information from top to bottom. Connectors are used as switches 1. in which,,,. Connectors 95-98 form the first cascade, connectors 99-102 - the second cascade, connectors 103-106 - the third cascade. To clock the switching system, a clock pulse generator 107 is used, from a group of outputs 108 of which clock pulses are sent to a group of clock inputs 20 (Fig. 1-13) of each electronic connector 95-106 (Fig. 15) entering the system. . The active subscribers 109-116 of the switching system (e.g., microprocessors) are associated with passive subscribers 117-124 (for example, with memory devices). FIG. 15 shows a variant of controlling inputs 19 (settings of electronic connectors 95-106 from one) of subscriber 116 on output 125. To input 15 of the mode of electronic connectors (Fig. 1) 103-106, forming the third (last) cascade, is constantly fed Tine 126 is a logical unit. A logic zero (not shown) is supplied to the input 15 of the electronic connectors mode 95- 102. In this case, vertical seams are used as address inputs of electronic connectors, and horizontal points are used as address outputs. Let the input priority be “About higher input priority”. Suppose that in a switching system it is required that 1 1 nonapiioe connect subscribers 109 1 121, 115 and 1 18, III and 123, IZ and 124. Binary numbers of passive subscribers with a given switching network configuration: 121-100 °, 118--0012. , 124-11L (Fig. 15). When switching from the information transfer mode to the setting mode (at the output 125 of the subscriber 116, a logical zero goes to a logical unit) all the switching elements of the electronic connectors 95--106 are turned off. In the first clock of the external clock generator i07, the switching takes place in the first stage and abone 1, 109, 111, 113, 115 put the logical signals "1," 1, "1," O. on their outputs. In the second cycle, the pa outputs of subscribers 109. 111, 113, 115 “O,“ 1, “1,“ O. In the third cycle, at the outputs of subscribers 109, 111, i; 3, 115 - - :( L, "o," 1. "1. At the end of the third cycle, according to the internal clock of TI 3, the connection path is fixed and, when passing s, the transmission mode The triggers are reset to the zero state by triggers 44 (Fig. 2). Their input is not pinned;; the organization of the connecting path from the third stage. For reference; the switching program is a trigger of the electronic connector 97, controlling the zero input connector with a single output ( in Fig. 15 uh, the switching element is conventionally shown as a square). electronic connector 100, controlling the connection of a single input with a single output, is reset to a zeroer) Oe state b. Yuka priorities (priority of higher input). Thus, the pairwise switching of the subscribers 09, 121, 115 and 118, 11 and 123 is carried out. Subscribers 113 and 124 are not connected due to the blocking in the commutation network (data links on php 15) are not shown. - logical address link m).

Invention Formula

Soedippte. The multi-stage COMMUNICATION of the system, the content of the matrix switch Kai-ia.TOB, the group of information inputs and the group of information outputs of which are cooTBCTCTBeiiHO gryngngami information {) pny inputs and kyhy.dov stroytev, matrix fixing connections size / rH, I The pynna from the lines of which is connected to a group of outputs for connecting the switch Biienjnei O and to the inputs of the canal control unit.: 1 line, the output of which is connected to the control inputs of the matrix canal switch. This is due to the fact that, in order to increase the speed of performance: 1, the reliability of the func tioning and expansion of the real possibilities due to the simultaneous 1) simultaneous, 1) search for and fixation of the number of channels in MHoroKacKa; iMoii com9

a mutation system, a matrix of address switches is entered into the device, the address groups of the first inputs and outputs of which are respectively the primers of the address inputs and outputs of the device, the address control block, address decryption block, confirmation send block, the mode input of which is the input of the device mode A confirmation receiving block, a priority block, a synchronization block, in which the setup input and the group of clock inputs are the setup input and the group of clock inputs of the device, the output state, respectively request fixing unit, a group of m information inputs of which is connected to the second group of information outputs of the connection fixation matrix, the first group of information inputs of which is connected to a group of information outputs of a priority block, a group of information inputs of which is connected to a group of information inputs the block of occupancy of the outputs and the third group of the n outputs of the connection fixation matrix, the second group of n information inputs of which is connected to the first group of n information inputs one occupancy block of outputs, the second group of n information outputs of which is connected to a group of n information inputs of the confirmation sending block, a group of n information outputs of which are connected to a group of n information outputs of the matrix address switch, a group of t information inputs of which are connected to a group from t information inputs of the acknowledgment receiving unit, a group of t information outputs of which is connected to the third group of m information inputs of the connection fixation matrix, four a group of m information inputs of which is connected with a group of m outputs block information deshifra1

ten

five

addresses, a group of m information inputs of which is connected to a group of information inputs of a matrix address switch, a group of mX "control inputs of which are connected to a group of mXrt outputs of a control block, addresses, the first group of mX information inputs of which are connected to the first group of tx "information outputs of the matrix of fixation of compounds, and the second group

0 from m information inputs of the address control block is connected to the first group of m outputs of the request fixing block, the second group of m outputs of which is connected to the fifth group of m information inputs of the connection fixation matrix, the first control input of which is connected to the first output of the synchronization block, the second the output of which is connected to the second control input of the connection fixation matrix, the first control input

Q confirmation confirmation block, the first control input of the confirmation receive block, the first control input of the address control block, the second control input of which is connected to the control input of the channel control block (1i and the third output of the synchronization block, the fourth output of which is connected to the first control input of the block of the output of the outputs, the third control input of the connection fixation matrix, the first control input of the request fixing block, the second control input of which is connected to the second control input of the direct connection unit confirmation memory, the second control input of the output occupancy unit, the fifth output of the synchronization unit and the fourth control input of the connection fixation matrix, the fifth control input of which is connected to the sixth output of the synchronization unit, the seventh output of which is connected to the third control input of the confirmation reception unit and the second the control input of the confirmation parcel.

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Claims (1)

Claim Connect.! - a multi-functional system containing a matrix switch of channels, a group of information inputs and a group of information punctures which are respectively groups of information inputs and outputs of a device, a matrix for fixing connections size τηχ, -ζ, the group of wxh outputs of which is connected to. a group of outputs for connecting an external switch and with the inputs of the channel control unit, the outputs of which are connected to the control inputs of the matrix channel switch, characterized in that. that, in order to improve performance, reliability of operation and expansion, functionality due to the simultaneous parallel search and fixing of an arbitrary number of channels in a multistage switching system, a matrix address switch is introduced into the device, the groups of address inputs and outputs of which are respectively groups of address inputs and outputs devices, address management unit, address decryption unit, confirmation sending unit, the mode input of which is the device mode input VA, acknowledgment reception unit, priority block, synchronization block, in which the tuning input and the group of clock inputs are respectively the tuning input and the group of clock inputs of the device, the output occupancy block, the request fixing block, the group of t information inputs of which are connected to the second group of t information outputs of the connection fixation matrix, the first group of n information inputs of which is connected to the group of information outputs of the priority block, the group of n information inputs of which is connected to drink from the n information inputs of the output employment block and the third group of η outputs of the connection fixation matrix, the second group of n information inputs of which is connected to the first group of n information outputs of the output employment block, the second group of n information outputs of which is connected to the group of n information inputs of the confirmation sending unit, a group of n information outputs of which is connected to a group of n information outputs of the matrix address switch, a group of m information inputs of which о is connected to a group of m information inputs of the acknowledgment receiving unit, a group of m information outputs of which is connected to a third group of m information inputs of the connection fixation matrix, a fourth group of m information inputs of which is connected to a group of m information outputs of the address decryption unit, group of t information inputs of which is connected to a group of t information inputs of a matrix address switch, a group of “Chi inputs of control of which is connected with a group of TXP outputs of a control unit phenomena, with addresses, the first group of TX information inputs of which is connected to the first group of TX information outputs of the connection fixation matrix, and the second group of 10 information inputs of the address management block is connected to the first group of m outputs of the request fix block, the second group of m outputs which is connected to the fifth group of m information inputs of the fixation matrix of ^1S connections, the first control input of which is connected to the first output of the synchronization unit, the second output of which is connected to the second control input the connection fixing matrix, the first control input 2Q of the confirmation sending unit, the first control input of the confirmation receiving unit, the first control input of the address control unit, the second control input of which is connected to the control input of the channel control unit and to the third output of the synchronization unit, the fourth output of which is connected with the first control input of the output busy block, the third control input of the connection fix matrix, the first control input of the request fix block, the second input is controlled ^{30 is} connected to the second control input of the acknowledgment receiving unit, the second control input of the output busy unit, the fifth output of the synchronization unit and the fourth control input of the connection fixing matrix, the fifth control input of ^{3 to} 5 is connected to the sixth output of the synchronization unit, the seventh output of which is connected with the third control input of the acknowledgment receiving unit and with the second control input of the acknowledgment sending unit. Fl i Fig.Z 31 6 25 ФЦГ.Ц Fig. 5 FIG. 7 Fig. /} Fig.9 Fig. U FIG. /1 FIG. 12 Fig.13 Fig.N FIG. fifteen