SU1226444A1 - Dividing device - Google Patents

Abstract

The invention relates to the field of digital computing, in particular to specialized computing devices for dividing, and can be used in modeling systems, automatic control, i.e. wherever it is necessary to perform the operation of dividing digit codes of numbers. The purpose of the invention is to increase the speed when dividing codes of numbers that are discrete values of continuously varying functions. A device for dividing it contains a frequency divider, two blocks of controlled summable reversible counters, two blocks of controlled subtractive reversible counters, a block for converting a direct code to an additional one, two three-input multi-digit adders, three two-input multi-digit adders, a multi-digit adder, an end fixation unit division, controlled frequency dividers, eight switches, eight reversible counters, four comparison nodes, and four combinator switches. New in the device is that it contains a frequency divider, two blocks of controlled summing reversible counters, two blocks of controlled subtractive reversible counters, a block of conversion of a direct code to an additional, two three-input multi-digit adders, three two-input multi-digit adders, a multi-bit adder, four controlled frequency dividers, eight switches, eight reversing counters, four comparison nodes and four combinational subtractors connected to each other links. 1 il. i SYA YOU 05 4 4 4:

Description

The invention relates to the field of digital computing, in particular to specialized computing devices for dividing, and can be used in various areas of the national economy, different modeling systems, automatic control, wherever it is necessary to carry out the operation of dividing n-digit codes of numbers. .

  The purpose of the invention is to increase speed. ,

The drawing shows the functional scheme of the device for dividing

The device contains a clock input of 1 device, a divider of 2 frequencies, two blocks 3 and-4 summation, two blocks 5 and 6 of subtraction, a direct code to additional converter 7, three three-input multi-digit adders 8-10, three two-input multi-digit adders 11- 13, element 14, the inputs of the codes of the sign 15 and the mantissa .16 are the device divider, the inputs of the codes of the sign 17 and the mantissa 18 of the divisible device, the outputs of the codes of the sign 19 and the mantissa 20 of the frequency device.

Each of blocks 3 and 4 of summation contains a controlled frequency divider 21, two switches 22 and 23 — two reversible counters 24 and 25, a multi-bit subtractor .26, and a comparison circuit 27.

Each of blocks 5 and 6 of the subtraction contains a control frequency divider 28, two switches 29 and 30, two reversible counters 31 and 32, a multi-bit subtractor 33, a comparison circuit 34.

The blocks of the device can be performed according to any of the widely known in the field of computer engineering circuits.

The summation blocks 3 and 4 and subtraction 5 and 6 are executed on reversible counters. Element And 14 is needed to fix the end of the division.

The device for dividing works as follows.

The dividend F, divider Au and frequency X are represented in the additional code and can be recorded as,,,, where a, f, x are the binary codes of the sign bits, respectively, of the numbers A, P, X5 a, f, X are the binary codes of the mantissas. these same numbers.

0

S

0

. s

0

five

0

five

0

In the initial state, all reversible counters of blocks 3-6 are cleared and on codes. Comparison of circuits of blocks 3-6 produces a signal that resets the corresponding controlled frequency dividers of blocks 3-6 and divides 2 frequencies through element 14

After submission to inputs 17 and 18 of a divisible code of the sign f and the code of the mantissa of the dividend f, the inputs of 15 and 16 of the divider of the sign code a and the code a of the mantissa divider on the first and second outputs of the adder 10 appear correspondingly. Codes X and X, at the first moment, are equal to the corresponding codes f and f of the dividend F, which arrive at the information inputs of blocks 3-6. Moreover, the information inputs of blocks 3 and 6 are received, respectively, codes, before) incendibly summarized in the adder 8 with the code a and the additional result-. with the code code a „and in the adder 9 with the codes a and a„. As a result, the comparison circuits of blocks 3-6 remove the signals that reset the divider 2 frequencies and the controlled dividers of blocks 3-6, and the clock pulses with a frequency f from clock input 1 arrive at the inputs of the reversing counters of blocks 3-6 and change the contents of the two-input multi-digit adders 11-13. There is a change in the frequent x and x codes, which occurs until the outputs of the block comparison circuits produce a Comparison signal, nulling frequency divider 2 and controllable frequency dividers of blocks 3-6. In this case, the desired frequency codes x and x are formed at the frequency outputs 19 and 20.

Claims (1)

Invention Formula A dividing device containing a frequency divider, an And element, two summation units, two subtraction units and the first second two-input multi-digit adders, the device clock input connected to the clock inputs of the frequency divider and all the summation and output blocks, whose frequency inputs are connected to the output of the frequency divider, the reset input of which is connected to the output of the element I, the inputs of which are connected to the outputs of the end of the summation of all blocks of summation and subtraction, which is characterized by the fact that, in order to quickly o-, act, a direct code converter is introduced into an additional, third two-input multi-digit adder and three three-input multi-digit adders, with the output of the sum of the first summation unit connected to the first, input of the first two-input multi-digit adder, the second input of which is connected with the output of the sum of the first subtraction unit, and the output with the first input of the second two-input multi-digit adder, the second input of which is connected to the output of the sum of the second summation unit, and the output with the first input ter its two-input multi value adder, a second input coupled to an output sum of the second .bloka subtractor, and an output - to the first input of the first adder trehvhodovogo multi value, the second and third the inputs of which are connected respectively to the inputs of the sign codes of the mantissa of the divisible device, the outputs of the codes of the sign and the mantissa of the private are connected respectively to the first and second outputs of the first three-input multi-digit adder, information inputs of the first subtraction unit and the second summation unit and the first inputs of the second and third three-input multi-slot single adders, the second inputs of which are connected - with the output of the direct code to additional converter, the input of which is connected to the input of the mantissa code of cases The device's device, the input of the divider's sign code, is connected to the third inputs of the second and third three-input multi-digit adders, the outputs of which are connected respectively to the information inputs of the first summation unit and the second subtraction unit. Compiled by E. Zakharchenko Editor T, Kugrsheva Tehred K. Kadar Corrector I. Erdeyi Order 2134/48 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4