SU1226402A1 - Device for generating signal which is proportional to velocity - Google Patents

Abstract

The invention relates to the field of instrumentation, automation and computer technology and can be used in digital software control systems that contain angle-code converters and in which the current value of the controlled value is set by absolute values. In this case, the problem of constructive simplification is solved. device and ensure its operation in the case of the presentation of the driver in parallel code. The output signal of the angle-code converter is fed to the first input of the device, i.e. on the first input of the adder and on the information input of the memory register. The output signal of the clock generator is fed to the control input of the memory register. In the memory register, the output signal of the angle-code converter is delayed by a quantization cycle. The output of the memory register is fed to the second input of the adder, and from its output through the elements 1 SHI and NOT the signal goes to the first input of the element I, the output signal of the error meter goes to the second input of the device, i.e. to the input of the decoder. It analyzes the mismatch signal and generates at its output a enable or disable signal that goes to the second input of the element I. The output signal of the AND element is through a frequency-voltage converter, for example, made in the form of a low-pass filter, and a high-power amplifier, for example, the basis of the operational amplifier, is fed to the output device. 1 il. i (L ГЧЭ ю О5 4 О Ю

Description

The invention relates to instrumentation, automation and computer technology and can be used in digital software control systems that contain angle-code converters, in which the current value of the controlled value is set by absolute values.

The purpose of the invention is to simplify the device.

The drawing shows a schematic diagram of the device.

The device contains a memory register 1, an adder 2, an EARS element 3, a decoder 4, an AND 5 element, a frequency-voltage converter 6, an amplifier 7, a first input 8 of a device5 a clock generator 9, a second input 10 and an output 11 of a device, a limiting element 12 , capacitor 13, operational amplifier 14, resistors 15 and 16, common bus 17, element NOT 18.

The converter voltage-voltage 6 contains a limiting element 125, a capacitor 13 and a common BUS 17 ,.

The amplifier 7 includes an operational amplifier 14, resistors 15 and 16, and a common bus 17.

The device works as follows,

When a device is connected to a converter, an adjustable value is a code, for example, a converter, a code whose output is connected to the information input of memory register 1, the information in which is updated at a frequency f fed to the control input of the memory register from the output of the clock generator 9.

Assuming that the maximum possible change in the regulated value over a period of 1 / f can also be recorded by bits of the binary code. Then the frequency of the change in state. The (h + 1) -th bit of the register of the dual converter counter is angularly proportional to the rate of change of the variable magnitude and is defined by the expression:

D

fQ,

where & q. increment of the angle-code converter code for the period of frequency „f

five

0

five

 capacitance h-bit binary counter transducer angle-code, frequency of the signal at the output of the clock generator 9. For generating a pulse of duration 1 / {at the output of the element NOT 18 when the state of the (+ 1) -th bit of the binary counter changes the angle-code converter input 8 of the device is connected to the output (P + 1) of the binary counter of the converter; call, r1 angle code. At the same time, the first input of the adder 2 receives information about the current state of the (h + 1) -ro bit of the binary counter of the angle-code converter, and the second - information about the inverse state of the (h + 1.) -Th bit of the binary counter angle-code converter, delayed for the period of the frequency signal f If the state of the (h + 1) -th bit of the binary counter of the converter-angle-code does not change over the specified period, t, e. the current information is equal to the information delayed for a period, then the output of the element is NOT 18 form 0

five

five

five

 0

if a

If the logical signal changes, then 1

Voltage pulses with frequency f hfoyd through element 5, receive a voltage-frequency converter voltage input 6, made, for example, in the form of ft-low frequency, constant voltage from the output of which is amplified by amplifier 7 and fed to the input of device 11, zero The base of which must be set by additionally introduced correction circuits, if a standard small integrated circuit is used as an element of And 5, the output voltage of which with the signal O differs from zero.

The voltage from output 11, in general, is summed with a voltage proportional to the mismatch between the setpoint and the actual value of the controlled variable, and is a control action for the controlled variable, slightly greater than the sufficient value. to maintain a given rate of change of the controlled variable.

A code proportional to the mismatch between the given and actual values of n {controlled variable, is fed to the input 10 and when it is reduced to a predetermined value

3

At the output of the decoder 4 and, respectively, of the element I 5, a signal O is set, which leads to a decrease in the voltage at the output 11 and an increase in the error.

The purpose of the decoder 4 is the switching off of the pulse voltage at the output of the frequency-voltage converter 6 at a mismatch lower than the allowable one, i.e. if the admissible mismatch code is 010, then with codes 001.and 000, at the outputs of the decoder 4 and element 5, respectively, a signal O arrives at the input of converter 6 of the frequency-voltage O. The value of the speed signal with a constant time of the integrating circuit begins to decrease and the mismatch is again increased to code 010. A decoder 4 has been implemented on IC K561 I112, to the inputs A of which the code from the PAC is supplied, and on the inputs B it is dialed with the help of a jumper;

The decoder circuit 4 is somewhat complicated if the SCP is built on the K572 PA2 DAC (with binary codes), since it becomes necessary to set the admissible mismatch code in both the positive and negative values.

With a binary code at the output of the angle-code converter, the memory register 1 is a D-flip-flop and the adder 2 and the elements OR 3, NOT 18 — the element EXCLUSIVE OR.

This is also true for the binary-decimal code 1248, if Q is 10,100 ... In this case, the input 8 of the device is connected to the low-voltage output of one of the decades of the angle-code converter. If it is required to have Qr 20,200 ..., then

264024

Input 8 of the device is connected to T, 3 and 4 bits of a decade angle-code converter, i.e. memory register 1 and adder 2 must be three-by-five. Receiving other Q values, with 1248 binary-decimal code, is difficult.

The proposed implementation of a device for generating a signal at 10 proportional speeds allows

simplify it significantly, and thereby reduce the cost and significantly increase its reliability.

Claims (1)

15 claims A device for generating a signal proportional to speed, comprising a memory register, an adder, The 20 clock generator, the elements OR, NOT, AND, and the limiting element connected by the first output to the input of the amplifier, the output of which is the output of the device, differs from the fact that, in order to simplify the device, it has a decoder and a capacitor, first the lining of which is grounded, and the second is connected to the first output of the limiting element connected to the output of the AND element connected to the decoder by the first input, and the input through the NOT input of the second input through the second input to the decoder output The output to the adder connected by the first input and the second inputs, respectively, to the information input and output of the memory register connected by yrtpaB- input to the output of the clock, generator, and the information input of the memory register and the input of the decoder are the first and second inputs devices. 40 Editor E. Papp Compiled by Y.Gladkov Tehred J.Popovich Proofreader M.Maksimishinets 2131/46 Circulation 836 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, st. Project, 4 Ll jJ .. II.