SU1223236A1 - Device fr debugging programs - Google Patents

Abstract

The invention relates to computing and can be used when debugging programs of a computer system in real time. The positive effect of the invention lies in the fact that it improves performance when debugging programs by allowing control of the next address of operands in the current command, previous addresses and operands, control and change the internal registers of the processor being debugged computing system, run programs from any address , set multiple addresses and break conditions. In the device containing the comparison unit, the element and the register and the multiplexer, a group of AND elements, a short pulse shaper, a trigger, a decoder, an OR element, and the first and second delay elements are introduced. silt i (/)

Description

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The invention relates to computing and can be used to debug computer programs in real time.

The aim of the invention is to improve the speed when debugging programs.

The drawing shows a block diagram of a device for debugging programs.

The device contains an input 1 for setting the start address, a multiplexer 2, a register 3, a group of 4 elements I, the first and second groups of information inputs 5 and 6, respectively, the first information output 7 of the device, the first clock input 8 of the device, the address input 9 of the device, outputs 10 and 11 device synchronization, the second information output 12 of the device, the comparison circuit 13, the decoder 14, the AND element 15, the first delay element 16, the second OR element. 17, the SHORT pulse generator 18 (FCI), the second delay element 19, trigger 20, initial setup input 21.

By the Initial Setup signal, which arrives at the input 21 when the power is turned on, a single pulse from the output of the circuit. The initial installation arrives at the R input of the trigger 20 and sets it to zero state.

A certain code corresponding to the number assigned to the program debugging device is written to the group of inputs of the comparison circuit 13. The device’s first input to the other group of inputs of the comparison circuit 13 receives the high-order bits of the address, which are compared with the code assigned to the program debugging device. When comparing with the output of the comparison circuit 13, a signal is received allowing the operation of the decoder 14 (to the third input of the decoder 14) and the 15.

At the first input of the device, the lower bits of the address arrive at the input of the decoder 14, and at the output 11 of the device, the control bus discharges to the input of the decoder 14. When a set of signals arrive at the decoder 14: the lower bits of the address, control bits and the signal from the comparison circuit 13, in

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Depending on the code received at the input of the decoder 14, one of the outputs of the decoder 14 is energized.

The incoming code can be four types. In accordance with the operation of the debugging program described below, we denote each of the codes by symbols: a, B, i. When entering the input of the decoder 14

10 code a, the first output of the decoder is energized. Upon receipt of the code, the second output of the decoder 14 is excited. Code 6 excites the third output of the decoder 14, which is connected to the first input of the element OR 17. Code ъ stimulates the fourth output of the decoder 14, which is connected to the second input of the element OR 17 and to the input of the short 18

20 impulses. The output of the latter is connected to the setup input of the S-flip-flop 20. The output of the OR element I7 is connected to the input of the delay element 19, the output of which is connected to the syncro25 sighting input of the C-flip-flop 20. Logic O is fed to the information input of the T-trigger 23 The presence of signals on the installation S and synchronization With the trigger inputs 20

30 transfers trigger 20 to a single state. The output of delay element 19 is the output of reference block 10.

The input 8 of the device to the element 15 is supplied with a clock signal. The operation of the element And 15 resolves the signal from the comparison circuit 13. From the output element And 15 signal is fed to the input of the element 16 delay.

4Q Multiplexer 2 provides switching of information coming from the first, second groups of information inputs (5 and 6) and from the first information output 7 of the device to the

45 second information output device 12 under the control of signals from the decoder 14.

Register 3 is designed to store information at the time of its

 transmissions through a group of 4 elements And to the first information output 7. A group 4 elements And is necessary to coordinate the information outputs of register 3 with the first information

 output 7 devices.

To debug programs, mini-computers (mic35

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ro-computer and debugged computer as follows.

The address bus of the mini-computer is connected to the group of address inputs 9 of the device, the control signals to input 8 and output 11 of the device, the data bus to the second information output 12 of the device.

The address and control buses (read / write signals, SIL - sync pulse of the active device) of the debuggee calculator are connected to the first and second groups of information inputs 5 and 6 of the device, respectively, the data bus is connected to the first information output 7 of the device, SIP signal line ( sync pulse of the passive device) - to the output 10 of the device.

The device works as follows.

The debugged computer in accordance with the organization of its interface, i.e. the address bus, control bus (read / write signals, SIA) and data bus are connected to the first and second groups of information inputs 5 and 6 and output 7 of the device, respectively. Bus 7 of the device is bidirectional. Output

The device includes a CIP signal line for the VPS debugged signal.

A mini-computer (micro-computer) used for debugging the calculator, in accordance with the organization of its interface, is connected by its address bus to the device’s address input group for debugging programs, the control bus to the control-input group 8 and the first control output

11 (signal SHI - sync pulse artist) device, the data bus to the bidirectional information bus 12 device.

The operation of the device for debugging programs begins with the fact that the mini-computer (micro-computer) exposes on its address bus, i.e. to input 9 of the device, a code and a synchronization signal to input 8 of the CXZ device (master clock). When analyzing these signals, the decoder 14 produces control signals determined by the code received from the mini-computer (micro-computer).

The minicomputer (microcomputer) at the beginning reads the control bus being debugged

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calculator For this, a mini-computer (micro-computer) supplies to the inputs one and two comparison units the corresponding code. According to this code,

5 the signal from the third output of the decoder 14 arrives at the second control input of the multiplexer 2, as a result of which the control bus of the debugged calculator switches

10 (the second group of information inputs 6 of the device) to the mini-computer data bus (the second bidirectional information bus I2 of the device), after the termination of transients in

15, multiplexer 2, decoder 14, on the first output, output 11 of the device, generates a sync signal for SHI. The mini-computer, when receiving a signal, the SCI reads the information received

20 Schuyu on her data bus, removes the signal of the CXS from bus 8, and then exhibited the code from the address bus, i.e. from the bus 9. The mini-computer analyzes the information received. If the numerator being debugged has set the read / write signal to the control bus, then it is necessary to analyze the address at which this operation is performed. The following happens. Minicomputer

30 exposes the CXS signal on buses 8 and 9 and the corresponding code to the input of the decoder 14. From the second output of the decoder 14, this code generates a signal from the first input multiplexer 2, resulting in the address bus of the debugging computer (the first groups of information inputs 5 devices) on the data bus of a mini-computer second bidirectional. information bus 12 device). Upon termination of the transient processes in multiplexer 2. decryptor 14, the sync signal for SHI is output. The minicomputer upon receipt of a signal by the SHI reads the information arriving at its data bus 12; removes the signal of SHZ on bus 8, removes you-; put the code from the bus 9 addresses. Mini-computer analyzes the resulting ad35

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If it is required to perform a write operation at the received address, then: the mini-computer exposes the CX3 signal on buses 8 and 9 and the corresponding code to the input of the decoder 14. A signal arriving from the fourth output of the decoder 14

to the third input of multiplexer 2, resulting in switching (via multiplexer 2) of the data pin of the debugged computer (first bidirectional bus 7 of the device) to the mini-computer data bus (second bidirectional information pin 12 of the device). After the end of the transient processes in multiplexer 2, the element OR 17, through the second delay element, generates a sync signal for the SHI. Min.and ZVM upon receipt of a signal, the SHI reads the information received on its data bus, removes the set code from the bus 9 address. The decoder 14 generates a CIP signal for the debugged computer, arriving at the output 10 of the device.

If, after receiving the address, it is necessary to perform a reading operation, then the mini-computer exposes the CX3 signal and the corresponding code to the decoder 14 on buses 8 and 9. From the output of the decoder 14, the signal arriving at the control input of the register 3 is outputted, resulting in recording information arriving at its information inputs from the mini-data bus (second bidirectional bus 12 of the device). After termination of transients in register 3, the decoder 14 of comparison generates a signal from its seventh output to the first group of inputs of group 4 of elements AND, resulting in information from: groups of outputs of register 3, entering to the second group of inputs of group 4 of elements AND, commutator) It is last on the debugged computer bus (to the first bidirectional information bus 7 of the device). After the end of the transient processes in the group of 4 elements AND, the SIP signal is generated for the debugged calculator at the output 10 of the device. From the output of the delay element 16 / to the output P of the device, an SHI signal is issued. The mini-computer, when receiving the SHE signal, removes the CX3 signal (device bus 8), the code from the address bus (device bus 9) and information from the data bus (device bus 12).

Thus, the proposed device provides significant

reduction of the program debugging time, since it allows to automate this process.

Claims (1)

Formula invented, shadow A device for debugging programs containing a comparison circuit. And a register and a multiplexer, the output of the comparison circuit is connected to the first input of the AND element, the address input of the device is connected to the first input of the comparison circuit, the second input which is connected to the input of the initial address of the device, the first information input of the device is connected to the first information input of the multiplexer, so that, in order to improve performance when debugging programs, a shaper of the short pulse, trigger, a group of elements And, the decoder, the element of the IPI, the first and second delay elements, the address input of the device connected to the first input of the decoder, the first and second outputs of which are connected respectively to the first and second controls l yuschimi multiplexer inputs, the comparison circuit output is connected to the second input deSchifratora third output is connected with the third control input of the multiplexer and the first input of the OR gate, the clock input device is connected to the third input of the decoder and a second input of AND gate whose output is through the first delay element is connected to the first synchronization code of the device, the fourth output of the decoder is connected to the register entry input, to the second input of the OR element, and through a short pulse shaper with a single trigger input, the direct output of which is connected to the first inputs of the AND elements of the group, the information outputs of the register are connected to the second inputs of the corresponding AND elements of the group, the outputs of which are connected to the second group of information inputs of the multiplexer and are the first group of information outputs of the device, the output the multiplexer is connected to the information input of the register and is the second information output of the device, the output of the OR element is connected to the trigger input of the trigger via the second delay element and is the second synchronization output of the mouth Compiler I.Sigalov Editor A.Schandor Tehred L.Oleynik Corrector C. Shekmar 1715/52 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Branch ShSh Patent, Uzhgorod, Proektna St., 4 device, the input of the initial installation of the device is connected to the zero input of the trigger, the information input of which is connected to the tire of zero potential.