SU1221702A1 - Method of starting direct frequency converter with artificial commutation - Google Patents

Abstract

The start-up method of a direct frequency converter with artificial switching is used for secondary power sources. The aim of the invention is to improve the reliability of the converter during start-up. A device implementing this method contains current-limiting reactors 1, a thyristor three-phase-three-phase direct frequency converter (NFC) 2, a network-led current inverter on thyristors (T) 5-10 s input-. with a smoothing reactor 11, switching thyristors (CT) 12-19 and capacitors 20-21. At the start of the start, a light pulse is generated and supplied to the reset thyristors (TC) 22 and 23, the voltage on the storage capacitor (NC) 28 is monitored. At the time the voltage reaches a predetermined value, the pulses are applied to the TC 22 and 23, simultaneously allowing control pulses to be applied to CT 12-19. After the supply of pulses to T 5-10, the further supply of control pulses to the NFC 2 is allowed when there is voltage on the NC 28 and prohibit it in case of its absence. The specified sequence of operations excludes the possibility of short circuit modes and unacceptable overvoltages on the thyristors of the converter than The reliability of the converter is increased at start-up. 1 il. tsD

Description

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The invention relates to electrical engineering and can be used in converter equipment.

The purpose of the invention is to increase the reliability of the converter during start-up.

The drawing shows a diagram of the device that implements the method.

The device contains current-freeing reactors 1, a thyristor three-phase-three-phase direct frequency converter .2, a diode transceiver bridge 3 for charging an artificial switching circuit, a reverse diode bridge 4, a network-led current inverter on thyristors 5-10 with an input smoothing reactor I1, switching thyristors 12-19 and switching capacitors 20 and 21, auxiliary thyristors 22 and 23 for dumping excess energy from the switching circuit, a sensor 24-27-current switching thyristors, storage capacitor 28, blocks 29-32 for resetting thyristors, switching thyristors, current inverter thyristors and non-intermediate frequency converter thyristors; the element OR 33, the inputs of which are connected to the outputs of the current sensors 24-27, the element NOT 34, the first element 35, the RS flip-flop 36, the starting element 37, the delay element 38, the input of which is connected to the output of the voltage sensor 39, the second element 40, the inputs of which are connected to the inverted output of the RS flip-flop 36, voltage sensor 39, and the third element 41, whose inputs are connected to the outputs of the delay element 38, voltage sensor 39 and the inverted output of the RS flip-flop 36. phase control thyristors reset connected to the starting element NMU 37 and the input element AND 40. Block input

30 impulse-phase control of switching thyristors connected to the output of the element 40. Block inputs

31 and 32 pulse-phase thyristor control of the slave of the current inverter and the direct frequency converter connected

to the output of the third element AND 41. The outputs of the blocks 29-32 of the pulse-phase control are connected to the control electrodes of the corresponding thyristors of the power circuit.

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The device implementing the proposed start method works; in the following way.

Trigger element 37 (usually this

5 a toggle switch or a contact, a relay) sends a signal to start the converter, which is fed to the first input of the first element 35 and the input of the pulsed control unit of the reset thyristors 29, where the passage of the starting pulse to the thyristors 22 and 23 is allowed. On the first inputs elements And 40 and 41 receives a signal / with the inverse output of the RS-flip-flop 36.

15 At this moment, signals from current sensors 24–27 are absent, since switching thyristors 12–19 are not switched on, which keeps element I 35 in its original state regardless of

The 20 states of the other inputs of the element 35. At the same time, the RS flip-flop 36 from the inverse output supplies the enabling signal. After the starting pulse is applied, the thyristors 22 and 23 receive a charge of the storage capacitor 28 and when the voltage reaches a predetermined value on the voltage sensor 39, the signal arrives at the delay element 38 and the second inputs of the elements 40 and 41. As a result, Element output 40 appears an enable signal, which is fed to the inputs of blocks 29 and 30 of pulse-phase control of reset thyristors and commutation to thyristors. In the absence of currents monitored by sensors 24-27, the signal at the output of the element OR 33 is missing and the element 35 is blocked.

With a delay of time determined by the delay element 38, the signal 41 is transmitted from the element 41 to allow the control pulses (blocks 31 and 32) to pass through the thyristors of the direct frequency converter 2 and driven by the current inverter on the thyristors 5-10. At the same time, a prohibiting signal appears at the output of the HE 34 element, which blocks the passage of commands at the output of the AND 35 element independently of the signals at the outputs of the OR element 33 and the starting element 37. After switching on the inverter driven by the network, in the case of at least one thyristor, the storage capacitor 28 is discharged and the signal from voltage sensor 39 is 35

40

50

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stops control pulses to all thyristors of the converter.

If the supply of pulses to switching thyristors 12-19 causes the appearance of switching currents, then this indicates a malfunction of the thyristors of the direct frequency converter 2. According to this factor, the signal passing through the element OR 33, element 35 at the start of the RS-flip-flop input 36 appears at the output of one of the sensors 24-27. At the same time, the inverse output of the RS-flip-flop 36 disappears at the inverse output of the RS-flip-flop 36 and the passage of signals through elements 40 and 41 becomes impossible, thus eliminating the emergency mode of a short circuit, accompanied by large currents. Before starting the converter, the RS-flip-flop 36 at the R-input is reset.

Thus, the sequence of operations indicated in the proposed method eliminates the possibility of short circuit modes and unacceptable overvoltages on the thyristors of the converter, which increases the reliability of the converter during start-up.

Claims (1)

Invention Formula The method of starting a direct frequency converter. With artificial switching, containing current-limiting reactors, a three-phase thyristor three-phase bridge with switching thyristors, two reset thyristers, a network-driven inverter 2217024 current and storage capacitor, which implies that control pulses are generated and fed to the switching thyristors 5 at the start signal and simultaneously generate a delay pulse of one period of operation of the direct frequency converter, generate three-phase thyristor control pulses of a three-phase bridge and a current-driven inverter , in the interval of formation of a delay pulse, they detect the presence of current in the commutating thyristors, serve pulses of control 15 or on the thyristors of a three-phase-three-phase bridge and a current-driven inverter after the formation of a delay pulse in the case of the absence of currents in the commutation thyristors and prohibits the supply in the event of a current being present in at least one of the switching thyristors, in order to increase the reliability , at the beginning of the start-up, the starting im- is formed and served. pulse to reset thyristors, control the voltage on the storage capacitor, when the voltage reaches a predetermined value, control pulses are sent to the reset thyristors, simultaneously allowing control pulses to be supplied to the thyristors, after supplying the pulses to the thyristors of the current-driven inverter, they allow further the supply of control pulses to thyristors of a direct frequency converter in the presence of voltage on a storage capacitor and prohibit it in case of its absence. 35