SU1215112A1 - Device for checking resources distribution - Google Patents

Abstract

The invention relates to the field of computing and can be used in modern high-performance computing systems. The aim of the invention is to increase the speed of the device and expand its scope. The device contains; register blocks, synchronization block, pulse distributors, multiplexers, comparison circuit, triggers, groups of AND blocks of elements, AND, OR, and BE elements. The device solves the problem of resource allocation between processes and analyzing deadlocks. 1 il.

Description

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The invention relates to computing and can be used in high-performance computing systems.

The purpose of the invention is to increase the speed of the device and expand its field of application.

The drawing shows a block diagram of the proposed device.

The device for controlling the allocation of resources contains the first block 1 of registers, the second 2.1- (I +1) -th 2 h blocks of registers of group 2 blocks of registers, block 3 of synchronization, the first 4, second 5 and third 6 distributors of pulses, the first controlling multiplexer 7, second (AND + 1) -th 8; h control multiplexers of group 8 control multiplexers, first 9 and second 10 information multiplexers, comparison circuit 11, first control trigger 12, match trigger 13, deadlock trigger 14, second trigger 15 control trigger 16 analysis, fourth 17 and fifth 18 trigger control units, the first group of blocks 19 elements And, the second 20, 1- (AND + 1) -th 20.-Ü group of blocks of elements And, the block 21 elements And, the eighth 22, the third 23, the eleventh 24, the first 25, the second 26 , sixth 27, fourth 28, fifth, 29, tenth 30, twelfth 31, ninth 32, thirteenth 33 and seventh 34 elements AND, fifth 35 and first 36 elements OR element OR-NOT 37, fourth 38, second 39 and the third 40 elements OR, the element NOT 41, information input 42 of the device, input 43 Start the device and output 44 of the device.

Register block 1 is designed to receive, store and issue process number codes that own the resources, and register register 2.1 to receive, store and issue process number codes that request resources.

The synchronization unit 3 is designed to synchronize the operation of the elements of the device.

The distributor of 4 (6.5) pulses is intended for dp forming at its outputs a sequence of h (1p, I) pulses distributed over time.

The control multiplexer 7 is designed to generate control signals depending on the information that is fed to its input.

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The control multiplexer 8.1 is designed to generate a control signal depending on the information received at its input.

, Multiplexer 9 is designed to form at its outputs one of a set of codes that arrive at its inputs 45.1-45. H, depending on the group of control

Q signals.

The multiplexer 10 is designed to form on the output bus one of the codes that arrive at its inputs (46.1-46.hi, 47.1-47.I,

5 depending on the groups of control signals.

Triggers 12,17 and 18 controls are designed to control the operation of the valves 4,6, and 5 impulses Q, respectively.

The trigger 13 coincidence is designed to fix the presence of the number of the analyzed process that owns the resource among the many processes

5 requesting resources, as well as to form a permission signal for selecting the next code of the process number that owns any resource. 14 deadlock trigger intended

 to form a dead end signal.

Control trigger 15 is designed to generate a signal indicating that the analysis resulted in deletion of processes. Analysis trigger 16 is intended

to form an end of analysis signal.

Group 19.1-19. And blocks of elements AND is intended for simultaneous transfer of information about the codes of the numbers of processes that own resources from the input of the device to the registers of block 1 of registers.

Group 20.1-20.h blocks of elements. And are intended dp simultaneous transmission of information on the codes of the numbers of processes requesting resources from the device input to the registers of blocks 2.1-2. h registers.

Elements 21.1-21.h are designed for forming the signals for setting the registers of registers block 1 to zero.

Elements 22,23,30,31,32,33 and 34 are designed to synchronize the operation of the elements of the device.

5 The element 23 is designed to form a signal that the control trigger 15 is set to the zero state.

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Element I 25 is intended to form a signal allowing the selection of the next code of the process number that owns any system resource.

Element And 26 is intended to form a setup signal into a single state of trigger 14 for deadlock.

Element And 27 is intended to form a signal indicating that the analysis had removed the processes.

Element And 28 is intended to form a signal for disrupting a new analysis cycle.

Element I 29 is designed to form an installation signal into one state of analysis trigger 16.

The OR elements 35 and 36 are intended to form the enable signal of the first and subsequent samples of the codes of the number of processes that own the resources, as well as setting the distributors of 5 and 6 pulses to zero.

The element STI-NOT 37 is designed for forming a signal that controls the operation of the element 25.

The OR elements 38 and 40 are intended to form the signals allowing the selection of the codes of the processes requesting resources.

The element OR 39 is designed to form a signal to set the zero of the distributor 6 pulses and the trigger 17.

The element HE 41 is designed to synchronize the operation of the distributor 4 pulses, the multiplexer 9 and the distributors 5 and 6 pulses, as well as the multiplexer 10.

The group of 42 information inputs is intended for receiving the number codes of the processes owning the system resources and requesting them.

The start input 43 is intended to give a signal, having started the operation of the proposed device.

The output 44 of the device is designed to detect the signal - a sign of a deadlock in the computing network.

The device works as follows.

In the initial state, all the triggers are in the zero state. The inputs of the initial installation on the figures conventionally not shown. A single signal from the fourth output of the synchronization unit 3 permits the reception of information

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matsii through groups of blocks of elements And 19 and 20 in block 1 of registers and group 2 blocks of registers. By the same signal, the control multiplexer 7 and the group 8 of the control multiplexers are closed, thereby prohibiting the mutual setting of the registers of block 1 and group 2 of blocks of registers to the zero state, respectively.

On the start signal (start of analysis); the input to the device input 43 allows the generation of control pulse sequences at the outputs of the synchronization unit 3, blocks the reception of information into the registers of unit 1 and group 2 of the register units, and allows overwriting information into: multiplexer 7 and group 8 of multi-ii plexors from the corresponding, register blocks . If the i-th register of block 1 contains a zero code, then the output. The i-th bit of the output group of multiplexer 7 produces a single signal, which is a signal to set to zero all the registers of block 2.1 of group 2 of blocks of registers. In addition, a single signal is output at the output of multiplexer B.j, for which all the registers of the corresponding block 2.J of group 2 register blocks store zero codes.

This signal is a zero-setting register signal of register block 1. The physical nature of these operations is to remove from further consideration processes that can certainly be completed and therefore will not lead to a dead end. Next, a transition is made to the identification of processes that are only the owners of certain resources, while they themselves do not request any other resources. If some process is only the owner of the resource, then its number should not be written in any of the registers of group 2 of the register register. The verification of this fact is based on the discovery of processes that only own the resources.

The analysis start signal at the device input 43 through the element OR 36 opens the element AND 22, the pulse from the first output of the synchronization unit 3 sets the trigger 12 to the one state, the signal from the single output of which opens the –I element 23. The pulse from the third output of the unit 3 synchronization through the open element AND 23 passes to the counting input of the distributor of 4 pulses, the signal from the first output of which allows through the multiplexer 9 the connection of the outputs of the first register of the register 1 to the first group of inputs of the comparison circuit 11. By the signal from the output of the element AND 23, the trigger 12 is set to the zero state and blocks the supply of pulses to the input of the distributor 4.

If the process code in the first register of block 1 of registers turned out to be zero, then element 25 produces a signal that initiates a transition to examining the contents of the next register in block 1 of registers. Otherwise, the zero signal from the output of the element And 25 is inverted by the element NOT 41 and through the elements OR 38 and 40 opens the elements 30 and 33, respectively. The impulse from the second output of the synchronization unit 3 through the open element AND 30 flip-flop 17 is set to one state and opens the element AND 32. By the impulse from the third output of the synchronization unit 3 through the open element And 33 the trigger 18 is set to single state and opens the element And 34 The next pulses from the first and second outputs of the block 3 synchronization through the open elements And 32 and 34, respectively, are fed to the counting inputs of the distributors 6 and 5 pulses. According to the signal from the output of the element 34, the trigger 18 is set to the zero state and blocks the supply of clock pulses to the input of the distributor 5 pulses. At the first outputs of the distributors 6 and 5 pulses, the signals that arrive at the inputs of the multiplexer 10 appear, providing connection through the output elements of the first register of the block 2.1 of group 2 of the register blocks to the second group of inputs of the comparison circuit 11. Then the distributor 6 operates. For each successive pulse of the first synchronization unit 3, the time-separated signals are sequentially generated at the outputs of the distributor, which control the slave via the second group of control inputs From the multiplexer 10. The multiplexer 10 selects the contents of the next register register 2.1 reg0

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ditch requests. If all requests to the selected resource have been exhausted, but no code comparison has taken place, then a signal is generated on the W + l) output of the distributor 6 pulses, initiating a transition to analyzing the requests of the next resource, which opens AND 31 and 33 through the OR 39 and 40 elements. The next pulse from the third output of the synchronization unit 3 through the open element And 31 is set to zero the trigger 17 and the distributor 6 pulses, as well as through the open element And 33 the trigger 18 is set to one and opens the element And 34. The next impulse From the second output of the synchronization unit 3 through the open element I 34 enters the input of the distributor 5 pulses, at the next output of which a pulse is formed, which through the first group of control inputs enters the multiplexer 10. At the same time, the signal O of the output of the And element 34 sets the trigger 18 to the zero state, as well as through the OR element 38 and through the open pulse from the second output of the synchronization unit 3, the E 30 element enters the single input of the trigger 17, which is set to the single state and opens element 32. When pulses are received from the first output of the synchronization unit 3, the pulse distributor 6 resumes its operation, which together with the pulse distributor 5 controls the sampling of requests to the next resource.

If during the sequential comparison with the codes from the registers of group 2 blocks of the request registers at least one coincidence occurs, i.e. if the process being studied not only owns the resources, but also requests them, the trigger 13 is triggered and set to one. This signal is used to select the contents of the next register of block 1 of registers, as well as setting the distributors of 5 and 6 pulses to zero. If, as a result of the analysis of all applicants for the selected owner, no matches occurred (the process in question does not request resources), i.e. trigger 13 is in zero state and

if the signal from the last output of the distributor 5 pulses is present, the element 27 turns on, which sets the trigger 15 to one state. At the same time, the signal from the output of the element 27 opens the element 21 of the block corresponding to the process under study and connects its output to the first group of control inputs of the register unit 1, thereby setting the register in which the code of the process under investigation is stored to the zero state. Through the multiplexer 7, the content of the corresponding block of group 2 of blocks of registers is corrected.

Similarly to the described analysis, the analysis continues until the end of the examination of the contents of the last register of block 1 of registers. The signal from the output of the distributor 4 pulses goes to the elements 28 and 29. If in this analysis cycle there were process deletions, then the signal from the single output of the trigger 15 opens the element 28 and the signal from which you set the distributor 4 pulses to zero through the element 35 of the distributor 35 5 pulses, through the elements OR 35 and 39 and AND 31 - the distributor 6 pulses, as well as through the elements OR 35 and 36 opens the element AND 22. By the pulse from the first output of the synchronization unit 3 the trigger 12 is set to one state and thereby initiates Alo new cycle of analysis.

If it turns out that in the next cycle of analysis of the deletions of the processes that can be completed, there was no element, And element 29 is triggered, the signal from which sets trigger 16 to one state. The analysis termination signal from the output of the trigger 16 is fed to the Stop input of the synchronization unit 3. In addition, the signal from the output of the trigger 16 is the enable signal for the And element 26.

If, as a result of the analysis, all processes in the system can be actually completed, all registers of register block 1 are set to the zero state. Consequently, there is no signal at the output of the control multiplexer 7 and element 26 does not trigger. The trigger 14 remains in the zero state. From the output 44 of the device, the deadlock signal does not issue

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Otherwise, the trigger 14 is set to one, and from output 44, a deadlock detection signal is output in the computing system.

Claims (1)

Invention Formula A device for monitoring resource allocation, comprising first and second register blocks, first and second pulse distributors, first and second control multiplexers, first and second information multiplexers, a comparison circuit, first and second control triggers, match trigger, deadlock trigger, analysis trigger, the first and second groups of blocks of elements are And, the block of elements is And, seven elements are And, the first element of ISC, element OR-NOT, and Information inputs of the first control multiplexer and the first information multiplexer, whose output rpjnnpa is connected to the first group of inputs of the comparison circuit and the group of inverse inputs of the first element And, Hi groups of outputs of the Second block of registers (where hi is the number of units of this type of resource) are connected to groups information inputs of the second control multiplexer and with the first to hi - th groups of information inputs of the second multiplexer of information, the output group of which is connected to the second group of inputs of the circuit is compared and, the output of which is connected to a single input of the coincidence trigger, groups of information inputs of blocks of elements of the first and second groups form an information input of the device, groups of outputs of blocks of elements of the first and second groups are connected respectively to groups of information inputs of the first and second blocks of registers, groups of outputs the block of elements I is connected to the first group of inputs of the reset of the first block of registers, the input of the initial installation of which is connected to the output of the second Control Multiplexer, the input of reset register block is connected to the first output of the first control multiplexer, the second output which is connected to the first input of the second element I, the device start input is connected by the first input of the first element OR, the zero inputs of the trigger and the analysis trigger, the unit output of which is connected to the second input of the second element I, the output of which is connected to the single input of the deadlock term, the unit output which is the output of the device, the unit output of the first control trigger is connected to the first input of the third element AND, the output of which is connected to the zero inputs of the first control trigger, the trigger coincides and the counting input of the first pulse distributor, the group H of the outputs of which is connected to the group of inputs of the NAND element, the group of control inputs of the first information multiplexer and the first group of inputs of the AND block, (H + D-ft the output of the first pulse distributor connected to the first inputs of the fourth and the five elements And, and the reset input - with the output of the fourth element And, the output of the fifth element And - with a single input of the analysis trigger, the output of the element AND-NOT - with the inverse input of the first element And, the output of which is connected to the second input The first element OR, the zero output of the coincidence trigger, is connected to the first input of the sixth element AND, the output of which is connected to the single input of the second control trigger and the second group of inputs of the block of elements AND, the output of the seventh element AND is connected to the counting input of the second pulse distributor, whose output group h connected to the first group of control inputs of the second information multiplexer, and (h + 1) -and output to the second input of the sixth element, And the unit and zero outputs of the second control trigger are connected according to With the second inputs of the fourth and fifth elements AND, moreover, in order to increase the speed and expansion of the device application area, the third one is entered into it - (h + 1) -and register blocks-, synchronization block, the third pulse distributor, third - (H + 1) -th control multiplexers, fourth and fifth control triggers, third - (i-tl) - a group of blocks of elements ten 15 0 five 5 0 5 0 0 Comrade I, six elements AND, four elements OR, element NOT, and Vrt rpyiin of the outputs of each of the blocks of registers from the third to (+ 1) -th are connected respectively to () T1 + 1) -th to. h fVn - by groups of information inputs of the second multiplexer of information and with groups of information inputs of the corresponding control multiplexers from the third to (M + 1) -th outputs of which are connected to the group of inputs of the initial installation of the first block. registers, the first output of the synchronization block is connected to the first inputs the eighth and ninth elements And, the output of the ninth element And is connected to the counting input of the third pulse distributor, the group hi of the outputs of which is connected to the second group of control inputs of the second multiplexer and information, (H1 + 1) -th output - with the first inputs of the second and third elements OR, the second output of the synchronization unit - with the first inputs of the seventh and tenth elements And, the output of which is connected to the unit input of the fourth control trigger, whose single output connected to the second input of the ninth And element, the third output of the synchronization block is connected to the second input of the third element And, the first inputs of the eleventh, twelfth and thirteenth elements And, the output of the thirteenth element And connected to the single input of the fifth trigger pack The unit output of which is connected to the second input of the seventh And element, the output of which is connected to the zero input of the fifth control trigger and the first input of the fourth OR element, the fourth output of the synchronization unit is connected to the control inputs of the first through (And + 1) th control multiplexers and second inputs of AND blocks from the first to (K + 1) -th groups, groups of outputs from the third to (11 + 1) -th groups of blocks of I elements are connected to the groups of information inputs of the corresponding blocks of registers from the third to (AND + 1) th inputs reset and which are connected from the third to () -th outputs of the first control multiplexer, the output of the first element AND is NOT connected to the second inputs of the third and fourth elements OR, the output of which is connected to the second input of the tenth element I, the first output of the output group of the first pulse distributor is connected to the jTOpbiM input of the eleventh element I, the output of which is connected to the zero input of the second control trigger; the first groups of inputs from the third to +) groups of I elements blocks are connected to the information input the device, the single output of the coincidence trigger is connected to the first input of the fifth OR element, the output of the sixth AND element to the second input of the fifth OR element, the output of which is connected to the third input of the first OR element, the second input the house of the second OR element and the reset input of the second pulse distributor, the output of the second the OR element is connected to the second output of the twelfth element AND, the output of which is connected to the zero input of the fourth control trigger and the reset input of the third pulse distributor, the output of the third element OR is connected to the second input of the thirteenth element AND, the fourth element MI The test trigger is connected to the Stop input of the synchronization block, the Start input of which is connected to the device start input, the output of the first WN element is connected to the second input of the eighth And element, the output of which It is connected to the single input of the first control trigger. | W / 7 {D / Ih LJ-1 L .J 20.P 2jj iZu Editor A.Lezhnina Order 907/56 Draw 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Branch PIP Patent, Uzhgorod, Proektna St., 4 Compiled by I.Khazov Tehred about. Nece-Corrector A. T sko