SU1211863A1 - Device for selecting and synchronizing signals - Google Patents

Abstract

The invention relates to a pulse technique, can be used for synchronizing signals from various discrete devices, including electromechanical ones. The purpose of the invention is to increase noise immunity and enhance functionality - by distributing the input signals over the output channels with a predetermined variable sequence. The device contains K5-TRIGGER 1, logic element AND 2, inverter 3, clock signal bus 4, input 5, vkho; 1, on 6. To achieve this goal B, the device was additionally introduced multiplexer 7, register 8, counter 9, decoder 10, prohibition element 11 and tire Reset 12. 1 Il. i (L

Description

Devices (-1 refers to the pulse technique, n can be used to synchronize signals from various discrete devices, including electrical ones.

The purpose of the invention is to improve noise immunity and to improve the functionality by distributing the input signals to the data channels with a predetermined time sequence.

The drawing shows an electrical schematic diagram of the device.

The device for separation and synchronization of signals contains the RS-trigger 5 element And 2, inverter 3, clock signal bus 4, input bus 5 and output bus 6, multiplexer 7, register 8, counter 9, decoder Yu, bar 11 and the trigger 12 Resetting the information inputs of the multiplexer 7 is connected to the input bus 5, the gate input - to the pin 4 of the clock signal, to the first input of the And 2 element and the input of the inverter 3, the output of which is connected to the gate input of the register 8, and the multiplexer output 7 is connected to the b-in RS - trigger 1, to the input of the prohibition prohibition 11 and with the counting input of the counter 9, the outputs of which are connected to the second, third, h th inputs of the register 8, second, third, h, and the outputs of which are connected to the control inputs of the multiplexer 7 and to the control inputs of the decoder 10 The outputs of which are the outputs 1-1 of the separation and synchronization device, while the direct output of the RS flip-flop 1 is connected to the first input of the register 8, the first output of which is connected to the second input of the AND 2 element, the output of which is connected to the decoder input of the decoder 10 and through element 11 of the ban - R-vho- Tzom R5-flop 1, the Shiva 12 Reset separation and synchronization signals device connected to vho- Tzom setting to zero the counter 9.

Multiplexer 7 has h input channels, with ti being equal to 2, Counter 9 contains ni binary bits, register 8 - ni +1 bits, and decoder 10 - m input channels to 11 output channels. In a specific device and 8., m 3.

The device works as follows.

When the power is turned on, the state of the counter 9, register 8 can be arbitrary. To set the device to its original state, it is necessary to apply a pulse signal to bus 12 Reset, while counter 9 is set to the zero state with subsequent reset in the clock pause to the zero state of register 8, R5 trigger 1 and the first bit of register 8 when power on is automatically set to zero.

Bus 4 is supplied with clock pulses with a duration b, and a pause duration. The zero code from the output of register 8 is fed to the control inputs of multiplexer 7, allowing reception of the signal on the first channel. When a signal appears in the first channel, a pulse is formed at the output of multiplexer 7, which coincides with the clock pulse on bus 4. Counter 9 is set to the first state, and RS-flip-flop 1 is set to one. At the end of the clock pulse, the information from counter 9 and from the RS trigger 1 is rewritten by the inverse clock signal into register 8. A single signal from the second output of register 8 allows element 2 to work, and the code from the output of register 8 to the control inputs of the decoder 10 prepares a second output channel. The closest clock pulse, the passage through the element I 2, enters the gate of the decoder 10, forms a single pulse in the second output channel and, passing through the prohibition element 11, resets the RS-trigger 1 to zero.

The trigger 1 is reset to the zero state under the condition that the prohibiting input of the 1 1 1 inhibition element is absent. If the output signal of the AND 2 element coincides with the signal at the output of multiplexer 7, priority is given to the signal from multiplexer 7, and the trigger 1 saves a single state.

The code from the output of register 8, arriving at multiplexer 7, includes the third input channel.

If the signal at the first input of the device continues to be present or appears again after the disappearance, the device does not react to it,

When a signal appears in the second input channel, the device will generate an output pulse matching the edges with a clock pulse in the third output channel, etc.

In this way, a successive connection of input channels, sequential reception of vx signals and the output of one pulse standard signal in the output channel is carried out at the input signal. At the input signal in the i-th channel, the device generates an output signal in the + 1st channel, and at the input signal in the last channel, a signal is generated in the first output channel and the first input channel is prepared again, thereby ensuring the interrogation of the input signals.

Thus, cyclical polling of input channels is provided in the device, and if there are no signals in any of the channels, the device blocks reception of signals from other channels, and the permanent presence of the device in one of the states may indicate a malfunction of one of the communication channels. In addition, when a signal arrives on any of the channels outside the loophole, which may be caused by the presence of interference in the channel by accidental, erroneous pressing of a button by the operator on the control panel, etc., the specified signal will not be perceived device that significantly povshaet pomehoustochivost reception and synchronization of asynchronous input signals.

The device also extends the functional capabilities by distributing input signals to output channels with a predetermined time sequence. For example, on input 1 si1: it arrived earlier than on input ch-1, but its duration is such that during its operation, a signal will come in channel i -1. Despite the fact that the signal to channel i was given earlier, the output signal, which was initiated by the response to this signal, was made later than

I Sosta Editor L. Avramenko Tehre

Order 650/60 Circulation 818 Subscription

VNIIPI USSR State Committee for Inventions and Discoveries

113035, Moscow, Zh-35, Raushsk nab. 4/5

Branch PPP Patent, Uzhgorod, st. Project, 4

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n | .1ho, a signal that reacts nn RF-one-iioi r signal channel -1.

The trigger 1, the element 2I, the element 11 of the prohibition on their connection can be excluded from the composition of the device, if only the edges of the input signals are synchronized.

Claims (1)

Invention Formula A device for dividing and synchronizing signals containing an RS-trigger, an H element, an inverter, a clock signal bus, input buses, and output buses, characterized in that, in order to increase noise immunity and enhance functionality by distributing the input signals to output channels with a predetermined time sequence, a multiplexer, a register, a counter, a deitfrater, an interdiction element and a reset bus are entered into the device, the information inputs of the multiplexer are connected to the input buses, strobe input - to the clock signal bus, to the first input of the element I and the input of the inverter, the output of which is connected to the gate input of the register, and the output of the multiplexer is connected to the S-input of the RS-flip-flop, and the prohibition input of the prohibition element and the counting input of the counter, outputs which are connected to the second, third, ..., nth register inputs, second, third, ..., h - outputs of which are connected to the control inputs of the multiplexer and to the control inputs of the decoder, the outputs of which are the outputs of the splitter and synchronization of signals, while pr m The RS output of the trigger is connected to the first input of the register, the first output of which is connected to the second input of the element I, the output of which is connected to the gate input of the deprafter and through the prohibition element to the R input of the RS trigger, and the bus with the installation input at zero counter. Proofreader I. Trdeyi.