SU1192072A1 - Device for controlling m-phase inverter - Google Patents

Abstract

A DEVICE FOR CONTROLLING A T-PHASE INVERTER, containing a stock angle adjuster, a switching sensor, a polarity sensor of supply voltage, the output of which is connected to the first inputs of the first and second elements AND and through the element NOT to the first inputs The second phase-shifting unit and the third and fourth elements And, the clock pulse generator, the output of which is connected to the second inputs of the phase-shifting blocks and the second inputs of the first and fourth elements And, reversible-sch The tweeters, the subtractor and the summing inputs of the first reversible counter are connected to the outputs of the first and second elements, And the subtractive and summing inputs of the second counter are connected to the outputs of the third and fourth elements, And the outputs of the meters are connected to the third inputs of phase-shifting units, characterized in that, in order to increase reliability of the inverter by ensuring the constancy of the advance angle S of the thyristors of the inverter, a one-shot, a controlled divider, an additional element NOT and an additional Our element, whose output is connected to the third inputs of the first and fourth elements, and the first input is connected to the output of the stock angle adjuster, the second input is connected to the output of the switching sensor, the second inputs of the second and third elements and, and to the input of the one-shot, the output of which the element is NOT connected to the third inputs of the second and third elements AND, the fourth inputs of which. connected to the output of a controlled clock-frequency divider, whose input is connected to the output of the clock generator.

Description

The invention relates to electrical engineering, in particular to converter switching control systems with network switching. The purpose of the invention is to increase the reliability of the inverter by ensuring the constancy of the angle ahead of the inclusion of the inverter thyristors. Fig. 1 shows a structural diagram of the device proposed in Fig. 2, 3 and 4 - timing diagrams of the voltages at the inputs of the elements of the device. . . The device consists of two identical channels of formation of pulses. Such a device structure for controlling jieHsf;) NIER grieving allows, separately for half-periods, to obtain a contour control, in which the gates (thyristors) of this inverter power circuit are produced depending on the signals received from the previous cycle of work of the same contour. . A control device (an n-phase inverter contains a set angle coal 1, the output of which is connected to the first input of the added additional element I2. The second input of the element I2 is connected to the second inputs of the second element IZ and the third element I4, as well as The output of the sensor is commutators 5 and the input of the one-shot 6, the output of which through the additional second element HE7 is connected to the third inputs of the elements IZ and IA, the first inputs of the second element IZ and the first element I8 are connected to the output of the half-period polarity sensor 9 and the first inputs TpeTbefo and the fourth elements I4 and I10 are connected to the output of the polarity sensor of half-periods 9 through the first .E11 element. The output of the I8 element is connected to the subtractive input of the first reversible counter 12, the output of the second IZ element is connected to the summing input of the same counter, the output of the I10 element is connected with the routing input of the second reversible counter 13, and the output of the element I4 - with the subtractive input of this counter. The outputs of the reversible meters 12 and 13 are connected to the third inputs of the phase-shifting blocks 14 and 15, respectively. The first input of the phase shifter; the guiding unit 14 is connected to the output of the polarity sensor of half-periods 9 directly, and the first input of the phase-shifting unit 15) to the output of the polarity sensor of the half-periods 9 through the HE element 11. The output of the clock generator 16 is connected to the third inputs of the phase-shifting blocks 14 and 15 and with the second inputs of elements I8 and I10, the third inputs of which are connected to the output of the input element I2, as well as through a controlled clock divider 17 pulses with quarter inputs of the elements IZ and I4. The divider 17 has a bus for changing the division ratio. The outputs of the device are phase shifting devices 14 and 15. Figure 1 also shows the power factor. Torus 18 and the power transformer 19. Figure 2 shows time diagrams of the voltages at the outputs of the corresponding elements of one of the channels. devices, when the signal duration. Well, from the output of the switching sensor 5 is less than the duration of the pulses Oms from the output of the one-shot 6, and the stock angle of the inverter is greater than the specified one, i.e. there is no temporal coincidence, a drop in the pulses Ug from the setting unit of the apaz 1 angle and U y from the output of the switching angle sensor 5. Figure 3 shows time diagrams of the voltages at the output of the corresponding elements of the device when the duration of the pulses Uip from the output of the switching sensor 5 is longer pulses il g from the output of the one-shot 6, and the temporal coincidence of the pulses Ui and {Jc is still missing. Figure 4 shows the time diagrams of the voltages at the outputs of the corresponding elements of the device when a temporary coincidence of the pulses O y and Ug takes place. Each of the channels of the device operates as follows. The reserve angle adjuster 1, synchronized by the supply voltage, forms, at the end of each half-period of the inverter-18 voltage supply, rectangular impulses V o, the duration of which is equal to the specified value of the safety angle S of the inverter (see Figures 2, 3, 4) . Pulses lit: from the output of the stock angle adjuster 1 is fed to the first input of an additional element I2, at the output of which there are no pulses. the duration of the pulses from the output of the switching sensor 5 supplied to the second input of the HE2 element is such that the actual stock angle — From the inverter gates will be greater than the specified stock angle 0, i.e. as long as b d, c h herewith, at the third input of the element I8, logical O, clock pulses to the subtracting input of the reversing account. Chica 12 is not served. The code from the reversible counter 12 at the beginning of each positive half-period of the supply voltage is rewritten in a phase-shifter unit 14 that generates control pulses of the inverter valves I, the phase of which is shifted relative to the beginning of the half-period by an angle Kin N and where / 3 is the angle ahead of the inverter. To the summing input of the reversible counter 12, the clock pulses do not fall while the inverted current of the inverter 18 increases to have such a value at which the pulse duration Y from the output of the switching sensor 5 depending on its value is less than the duration of the pulses 6. At the same time, at the second and third inputs of the second element IZ there is no temporal coincidence of logical 1, When with a further increase in the current the duration of the pulses (J g from the output of the switching sensor 5 becomes longer than the duration of the pulses C the output and one-shot 6 (see Fig.3), there is a temporary coincidence of logical units from the outputs of the switching sensor 5 and the second element HE2 at the second and third inputs of the second element FROM, which leads to passing to the summing input reversible counter 12 clock pulses.ot generator 16 through a divider 17. The code in the counter 12 is increased, which leads to an increase in the ignition angle of the inverter valves and a decrease in the actual angle of the stock 5d, of the inverter valves 18. The divider 17 has a bus for changing the division factor. Therefore, the code change in the counter 12 can be maintained by controlling the division factor from the digital computing device and taking into account the operation area of the inverter, value 6, etc. The actual stock angle decreases until it reaches the specified stock angle Sj (see Fig. 4) formed by the set angle of stock 1. At Sqj s & 3 (figure 4), the inputs of additional element I2 coincide in time Ug pulses from the set angle generator 1 and pulses from the output of the switching sensor 5. The presence of a logical unit at the output of element I2 leads to the passage of pulses from the clock generator 16 through the first IW element to the subtracting-1 input of the reversing counter 12. Since the frequency of the generator pulses is 16 much higher frequencies If pulses are output from divider 17, then reversible counter 12 begins to change the code Gd so that a further decrease in the actual stock angle stops and the inverter 18 starts working with a constant stock angle equal to the set value of the stock angle Sg. The operation of the second channel of the device, synchronized with the negative half-period of the supply voltage, proceeds similarly to the operation of the first channel. The effectiveness of the device is to increase the stability of the inverter, i.e. in preventing the possibility of its tilting at the moment of the beginning of entering the inversion mode due to the fact that the entrance to the inversion mode is not with a constant stock angle, but with a constant angle of advance of the inverter valves, which eliminates in the regulated system positive feedback inverter current and causes negative feedback, thereby reducing the rate of rise of the inverted current.

FIG. Z

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P 2Ya ZUG (t

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Claims (1)

DEVICE FOR CONTROL OF TN-PHASE INVERTER, containing a reserve angle adjuster, a switching sensor, a polarity sensor. Half-periods of the supply voltage, the output of which. connected to the first inputs of the first phase-shifting unit and the first inputs of the first and second elements And and through the element NOT to the first inputs of the second phase-shifting unit and the third and fourth elements And, the clock generator * whose output is connected to the second inputs of the phase-shifting blocks and the second inputs of the first and the fourth element And, reverse-counters, subtracting and summing the inputs of the first reversible counter are connected to the outputs of the first and second elements And, subtracting and summing the inputs of the second counter s with the outputs of the third and fourth elements And, the outputs of the counters are connected to the third inputs of the phase-shifting units, characterized in that, in order to increase the reliability of the inverter by ensuring the constancy of the lead angle of the thyristors of the inverter, a one-shot, controlled divider, an additional element NOT and additional element And, the output of which is connected to the third inputs of the first and fourth elements And, the first input is connected to the output of the reserve angle adjuster, the second input is connected to the output of the commutator sensor the second inputs of the second and third elements And and to the input of the single-vibrator, the output of which through an additional element is NOT connected to the third inputs of the second and third elements And, the fourth inputs of which are connected to the output of a controlled clock frequency divider, the input of which is connected to the output of the clock . SHI1 ITS 1 1192072 ²