SU1190525A1 - Device for decoding code - Google Patents

Abstract

1. A DEVICE FOR DECODING CODE containing first and second adders, calculator of parity, decoding failure block, multiplier, code generator, equalizer, error detection block to the first block of adders, the input of which is combined with the first input of the parity calculator, information input the corrector n is connected to the first input of the device, and the first output is connected to the first inputs of the error detection block, the code generator and the first adder, the second input of the parity calculator is connected to the second input of the device and the output is with the first input of the decoding failure block, the first output of the offset is the first output of the device, the output of the block of failure from decoding is the second output of the device, the output of the first adder is connected to the first correction input of the offset, the second correction input of which is connected to the output of the second an adder, to the input of which is connected the output of the code generator, the output of the error detection block is connected to the second input of the decoding failure block and is the third output of the device, which is different By the fact that, in order to increase the speed and reliability of the processed information, the second and third blocks of adders, the backward root calculator, the excluded code generator and the parity corrector, the first input of which is combined with the second input of the device, are entered into it, the second input is combined with the second input of the detected block error and is connected to the output of the parity calculator, the third input is connected to the output of the error detection block, the fourth input to the output of the decoding failure block, and the output is the fourth output of the device The first input of the second block of adders is combined with the inputs of the first and third blocks of adders, the second input is connected to the second output of the first block of adders, and the output is connected to the first input of the multiplier and the second input of the code generator, the output of the third block of adders and the second input of the multiplier, the third input of which is connected to the first output of the first block of adders, and the output to the input of the backward calculator, the first output of which is connected to the third input of the imager codes, the output of which is connected to the second input of the first adder, the second output of the backward calculator is connected to the third input of the decoding failure block, the fourth input of which is connected to the output of the excluded code generator, the first input to

Description

The second input is connected to the output of the first adder, the second input to the output of the second adder, and the third input to the second output of the equalizer, the control input of which is connected to the output of the error detection unit, the output of the multiplier is connected to the fifth input of the decoding unit.

2, The device according to claim 1, wherein the equalizer contains an AND-OR-NOT block of elements, an adder block of inverters, first and second high-order decoders, first and second low-order decoders, the control inputs of which are combined

and connected to the control input of the corrector, the first correction input of which is connected to the information inputs of the first decoders of the junior and senior bits, and the second correction input - to the information inputs of the second decoders of the junior and senior bits, the outputs of the decoders through the AND-OR element block - NOT connected to the first input of the adder, the second input of which is connected through the inverter unit to the information input of the corrector, and the output to the first output of the corrector, the outputs of the decoders are connected to the second output of the coder Rector

3. The device according to paragraphs. 1 and 2, characterized in that the reverse root calculator contains low and high order decoders, a block of AND-OR-NOT elements, a block of AND-NOT elements and a decoder zero, whose input is connected to the output of the block of AND-NOT elements and the first output of the calculator reverse roots, the input of which is connected to the inputs of the low-order and high-level decoders, the outputs of which are connected to the corresponding inputs of the element block .. AND-OR-NOT, the output of which is connected to the input of the AND-NOT element block, the output of the zero decoder is connected to the second output of the calculator Backward roots.

4. Device on PP. 1-3, characterized in that the driver of the excluded codes contains the first, second, third and fourth elements AND and the first and second elements OR, the inputs of the first and second elements AND are connected respectively

with the first and second inputs of the driver of the excluded codes, and outputs with the first inputs of the first and second elements OR, respectively, the second inputs of which, as well as the first and second inputs of the third and fourth elements AND, are connected to the third input of the driver of the excluded codes, the outputs of the third and fourth elements AND connected to the third inputs, respectively, of the first and second elements OR, the outputs of which are connected to the output of the driver excluded codes.

5. Device on PP. 1-4, which is based on the fact that the parity corrector contains the first and second AND elements and the adder, the first input of which is connected to the first input of the parity corrector, the second input of which is connected to the first input of the first element And the third and fourth parity corrector are connected

with the corresponding inputs of the second element And, the output of which is connected to the second input of the first element And, the outputs of the elements And and the second and third inputs of the parity corrector are connected to the corresponding second inputs of the adder.

The invention relates to computing and can be used in systems for processing, storing and transmitting information, in particular in high-speed memory devices with parallel writing and reading.

The aim of the invention is to improve the speed by accelerating the code word in the absence of errors and the reliability of the processed information by using, when selecting from decoding}, the facts of not solving the quadratic equation and the presence of excluded locators

FIG. 1 is a block diagram of a device for decoding a code; in fig. 2 is a block diagram of a corrector; in fig. 3 is a block diagram of the evaluator of reverse roots.

The device for decoding the code contains the first block 1 adders, the second block 2 adders, the third block 3 adders, the calculator 4 parity corrector 5 parity 5, the multiplier 6, the error detection block 7, the calculator 8 reverse roots, the decoding failure block 9, the first adder 10, corrector 11, shaper 12 codes, second adder 13, shaper 14 excluded codes, first input 15, second input 16, first output 17, second output 18, third output 19, fourth output 20. Corrector 11 contains the first decoder 21 older bits, first decoder 22 low bits of the second decoder 23 low bits, the second decoder 24 high bits, block 25 elements AND-OR-NOT, adder 26 and inverter 27. The calculator 8 reverse roots contains the decoder 28 high bits, the decoder 29 low bits, a block of 30 elements AND-OR-NOT, a block 31 of ele- ments of AND-NOT and a decoder 32 zero. Shaper “14 excluded codes contains the first, second, third and fourth elements AND 33-36 AND and the first and second elements OR 37 and 38. The parity corrector 5 contains the first and second elements And 39 and 40 and the adder 41. The error detection unit 7 contains the OR elements 42-45, and the decoding reject block 9 are the OR elements 46-48, the AND elements 49 and 50, and the adder 51. One connection of FIG. 1-3, there are several electrical connections. For example, from the input 15, the output 17, and the outputs of the block 25, tires depart t7 -1 wide. From the first output of block 1 and from the outputs of block 3 and multiplier 6, adder 10, adder 13, waste t 2t-bit tires (t-bits - direct values of signals of bits and inverse values). From the first output of the number 8, move the g (t-1) to the bottom of the tire. From the exit of the driver 12 leaves 42-bit bottom tire.

The device works as follows.

The operation of the device is described for the case when the number of information bits and the length of the code being decoded is n t79, i.e. 15 bits are checkable. The information enters the device and is transmitted between the blocks in parallel form. A decoded 7-9-bit word a (ao, a |, ..., arg), which, possibly, contains errors, goes to Inputs 15 and 16 of the device. In this case, the evenness check bit a is fed to the input 16, from where it passes to the calculator 4 and the equalizer 5, and the remaining bits a ..., a, and to the input 15, from where they pass to blocks 1-3, the calculator 4 and corrector 11.

When the device operates, each bit of the decoded word a is associated with a discharge locator, which is an element of the final Galois field GF (2). This field contains 128 items. The N element of the GF (2) field is represented by either a set of seven binary bits.

N (N ,, ..., N, N.),

(one)

or by the polynomial N (") ..

,

where N; e {0,1,

. te is the primitive element of the field GF (2), which is the root of the polynomial x + x + 1. The + sign hereinafter denotes addition modulo two (for vectors, bitwise addition modulo two). For error correction, the device calculates distorted bit locators: first error locator i, second error locator i.

Error locators are configured as follows. For the decoded word a, block 1 calculates the sum of the error locators S xii + ig, block 3 calculates the sum of inverse locators $ 2

S - + -, calculator 4 calculating 1., 12

There is a parity check for P. If S, and, then there are no errors in the word a. If S 82 O and, then there is an error in the discharge of a. If 5 ,, Sj / 0, -g- SgCT.e. 8,) and then

there is one error in the category with i | S,. If S, 4f O, S and, TO there is an error in the range of the locator and, in addition to the error in the discharge of a. Finally, if S, O,, and, then it is assumed that there are two errors in the bits, ..., and with locators i I, i. In all other cases (in particular, if 5 ,, Sg О, or S, 0,, or 8.0,, 5.82 / 1,), decoding decoding must be refused, since the number of errors is equal to or greater than three. In the case when,, S, 8jf1, and, error locators i, are calculated by solving (in multiplier 6, calculator 8, adder 10, driver 12 and adder 13 the system of equations over the field GF (2) + 12 S, H - 2 To solve system (2), the square root equation k is calculated first. 1- О, SjSg. M multiplier-6. In this case, multiplying the value of 8 in the GF (2) S field. The calculator 8 is the reciprocal of the free member finds 3 the root X of the quadratic equation (3) or determines that equation (3) has no solutions. In the latter case, the device refuses to decode. The rectifier 12 and the adder 13 multiply the root x by 8 and form the first error loop i, x8. In parallel, use intermediate results, the former 12 and the adder 13 form the second error locator G The corrector 11 corrects the distorted bits using the values of locators ij and i. If an error occurs in bit a, it is corrected in corrector 5. Block 7 detects errors comparing to zero value 8; and 82. Blo 9, using information from corrector 5, block 7, calculator 8 and form l 14, generates a decoding failure signal in the presence of triple errors and phased error packets of length 4. Decoding the word is executed in the device, taking into account that the code The (unmistakable) word a (a, a ,, ...,) is formed with the help of a matrix K consisting of three K ,, Kg, Cr submatrices given in Table. 1. In word a, bits a, a, ..-,.; 40 e, e, a, 2 4c test, the remaining bits - a ,, ..., H 3 (EZ, a-jg - informational. To each; the pro of the eV an OTHER level corresponds in the matrix To the column with one unit i the line containing this unit indicates (with its own units) which information bits are involved in the formation of the given check digit. For example,, + +,.. + a-fg i ,, + a, +. +..... +. + a „+ Matrix K, when decoded, corresponds to a test matrix H, consisting of three submatrices H, H, Hp and is given in Table 2. (Table 2 also shows that from the input 16 bits d / l on i-th p the input of block 1,, ..., 78). Each column of the matrix N. is the locator of the corresponding digit of the word being decoded A. The locator of the discharge is a seven-bit binary set - the element of the field GF (2). Each column of the matrix Hg is the element of the field GF (2), the inverse of the corresponding locator, i.e. if the column of the matrix H | is the element 1 of the field GF (2), then the corresponding column of the matrix H is the element of floor GF (2). The matrix Hn is a string of 79 units and provides the parity of the decoded word. Block 1 calculates, (8f6, ..., 8i,, 8, е,) (4), by multiplying the word (O, a ...,) by the transposed matrix Kc, realizing (S, j,. .., 84,) (0, a /, ...,) Hj, where T is the sign of the transposition of the matrix. The multiplication of the vector by the matrix is realized with the help of modulo-two adders, which, if necessary, have direct and inverse outputs. For example, d; military bits S, g, 8 are formed as follows: S, ..., S, y. . . . + a j + ajy + .., + afg, i.e. when forming the i-th bit of the product, the modulo-two sum of those bits is calculated; these are the words a, whose numbers correspond to the unit elements of the i-th row of the matrix. Due to the fact that the number of inputs of the modulo-two input does not exceed 8 or 9, the implementation of the vector multiplication per matrix usually gives intermediate sums A at first: from 8–9 terms, from which the clocks form . So, to get S | 6 and 8.5, you can first form the sub-sums A | 48 "S5 2 96 AZ 4h + ...; A.4 ... + arg, A a; 2 + ... + a; 9, 6 and then the bits of the product 8f6 A, H-Aj + A + A; , -bAg + A4. Block 3 using modulo-two adders with direct and inverse outputs included in its composition calculates the sum of inverse locators 8, which is an element of the GF field (2 17 by multiplying the word (o, a {, ..., on the transposed matrix 2. Block 4 with the help of modulo-two adders with direct and inverse outputs. Included in its composition, calculates a parity check P, realizes the ratio P (ao, a |, ..., a / g) + a, + ... a I. Block 2, in order to prepare multiplication in multiplier 6, calculates six pairwise sums of binary components in multiplayer 12 and adder 13 The values of 8 j Uj 8, j +8, (j4,); j 1, ..., 5,, 6 + In this case, the quantities U2, ..., U, which are used in the multiplier 6, are calculated directly from the deco simultaneously with the value 84. This allows multiplication to start in multiplier 6 immediately after calculating 8, Szt which shortens the decoding time. Computation and, ..., Ug is performed in block 2 using modulo-two adders by multiplying the word (o, a, .. ,,) on the transposed matrix N4, given in Table. 3. At the same time, the relation, (Ug, ..., U "φ (o, a ..., a; c) (5) is realized. Intermediate results of summation A can be used to implement hyphenation (5) in block 2; , -produced in block 1 in the implementation of expression (4). For example, Uj A, Aj + A + Aj + Ag. These intermediate results Aj are received in block 2 from the second output of block 1. From the same output in block 2, binary components arrive. the values of S needed to form those sums Uj; which are used only in the driver 12. In the case under consideration, this is 8 (by which U, 8 ,, +8 | 2 are multiplied by Multiplier 6, and in the GF (2) field, the value of UU is multiplied by S by Sj, yielding the value (gg, .. el Еоo. With the help of AND-NOT and NOT logic modulators with direct and inverse outputs, included in the composition of the multiplier 6, the relations are implemented., + Sg Ug + 8; 8 „+8 - 8 and -1 - E 4-QQ LGS- 2. go and .CB -5„ S ,, + + & 22 12 Sj, 8 (, and., +82, and, -f and + - ..- .z-. -If spv sTVFWi s T y (g 13 g. + SJ, S, rt S TSf Jl TUa- sITUs -s, u -, - s, 8 (S7gS ((+ 8gy 8, g, +8, 8.4 +, g is the inverse of the free term of the quadratic equation (3) This equation either has two solutions and y, or has no solutions. At the same time, the solutions and y, which are elements of the field GF (2), have the form x (x ,, ..., Xj, X ,, 1) , y (Xg X, X ,, 0), i.e. the solutions are different from each other only in the component N. (1). The calculator 8 determines whether the equation (3) is perturbed and solves this equation. If the solution is, then on the jBTopoM output of the calculator 8 the discriminant is fortified, and on the first stage the binary components of the solutions, ..., Xg If there is no solution, then at the second output, a value is generated, and zeroes are output to the first output. In cases where (i.e. in the case of a one-time error) and when (i.e., in the absence of errors or in the presence of multiple errors ), equation (3) has no solutions and zeroes are output to the first output. In shaper 12 and adder 13, the locator of the first error ошибки is calculated by multiplying the root by Sj. In this case, the driver 12, using the AND-NOT elements included in its composition, calculates a 21-part product of the form h, - x, -Sjj, 2, ..., 7-m,, 2, ..., 6, and a 21-part product of the form ij, ..., 5,6; .,. .., 6. The adder 13 with the help of modulo-two adders with the direct and inverse outputs included in its composition calculates the binary components of the locator of the first error i. (I -16 M. 1 S t I, 1,), With this realization vfazheny i | 6 1bb. + h42 + ll ,, + h ,, 4 + h, 5 + S, 6 i ii5 1b5 + l56, + h, 4 + S, f / i And 1b4 + h ,, + S and; LZ 1bZ + l45 + b, + h, 2 +81,, iiz -l62 + lf3 144 + 135- + 1gb + h; ,, + S, 2 j 1bg -H + 1-13 + IM +1 + 1 / 9 + s ,,; i / o & i + 52 + ti43 3t 2 + (If or, TO arrives at input of form 12 from calculator 8, zeros arrive and locator i Sj is formed at output of adder 13. Adder 10 with modulo two adders and inverse outputs included in its composition, calculates the second error locator ,, ,,., iyi, 1), while implementing the simulations, + b42 + b, 2-i6f + l5-e + h4f + h92 + h25 + h , 44 H U + iM-l s-l e + hj. + H ,,, i-1., + 1--Ьba + 1 h - + 1 ос + Ь; i2r 1b1 + 152-11Y1 4 + 12 + 1-.6 i-7n ht. + h "+ h4a + li44 + h, + h Block 7 detects errors, comparing the values of S, S and P with zero. In doing so, using the logical elements AND, OR, and NOT included in block 7, the relations are calculated, Binary binary signals F, Pr F F о o FS, V ... VS,., VSj о, if Sj 0 l, if S 0, j 1,2 (7) F, if Nj, g 0 1, if, (8) where N, o number of errors in the bit -. about i / dah a. , .. ", V is the sign of a logical operation OR 0 if there is no error in word a 1, if there is an error in word a. (9) Signal Wt, from the output of block 7 enters output 19 for use in the system including the de, coder. The signal F from the output of block 7 is fed to the inputs of the equalizer 5 and block 9, as well as to the control input 15 of the equalizer 11. The signals F., F are fed to block 9. The corrector 11 decrypts locators i ,, 12. and corrects bits a, ..., but . The locator ii, which is fed to the second correction input of the equalizer 11, is divided into two parts. The Mlad-™®RI of the discharge (i,. ,,,, i / d) is fed to the information input of the decoder 23, and the older four bits (ij i (5 Gz) from the information- "input of the decoder 24. Similarly, the older the locator bits (ig, iy ,,) come from the second corrective input of the offset 11 to the decoder 21, and the lower bits (, 12, izo) to the decoder 22. The signal F from the control input of the offset 11 goes to the control inputs decoders 22 and 23.

If then deymfrators 22 and 23 are open, In this case, decoder 23 forms the binary word word L (b, b, ..., b) with one unit in the bit corresponding to the code on the information input of the decoder. Similarly, the decoder 22 forms an 8-bit word with one unit of f (fo, f ,,, .., decoders 21 and 24 Form 16-bit words with one unit of U (UQ, U ,, ..., U, respectively 5) and m (m, m, ..., M, y) The words b, f, u, m from the outputs of the decoders 21-24 enter the block 25 and, moreover, pass to the second output of the corrector 11, from where in the shaper 14.

Block 25 forms inverse correction word Е (Е,, ..., Ey). . The binary signal, if the first correction input or the second correction input of the corrector 11, received a j-ro digit locator. Otherwise, the signal Ej 1.

Thus, in block 25, the second decryption stage and the combination (OR) of the corresponding signals is completed. In the adder 26, the bits a.,. ,, ..., are corrected and corrected by implementing the ratios aj a, E :; , 2, ..., 78.

J J J / f

If there are errors in bits,

e

No, the signal and the decoders 22 and 23 are closed. In this case, regardless of the signal values at the corresponding inputs, zero words are formed at the outputs of the decoder 22 and 23, and the correction word E consists of units E (1, ..., 1). Bits a | , ..., aj.g is passed to exit 17 without change.

If the locator r or i is an inclusion (the field element GF (2) is not used as a locator) and .. there are errors in the bits aj, ..., then it is necessary to refuse decoding. This is performed by shaper 14. It analyzes whether ij, 1 "are excluded, and generates signals Z, 2 in accordance with the expression

go

if locator ij is not excluded

P-. if locator ij is excluded.

Shaper 14 implements the relationship

Z, 1,5 L, VUgVU, 2 VU ,, bg, - (10)

Zj i .., Vm, fg, (11)

The signals Z, Z are received in block 9, which with the help of modulators two and logical elements AND, OR, NOT, which are included in its composition, generates binary signals BuW

... v, vi;

(Oh, if g is 1, 1 if g; "1; (12)

W (F, + F) VFB () VFZ

0 if the output is 17 corrected word

1, if decoding is refused (13

FB 1 in the case when at least one S. O and. Refusal to decode when and S, 5 o; provided by a member. If S 0; , g 1 1, then decoding failure is generated in any of the three situations:, equation (3) has no solutions,, locator iy is excluded, the number of errors is odd. In addition, decoding failure is generated regardless of the value of g, if, S and Z | 1 (i.e. locator ij - excluded).

Corrector 5 adjusts the bit, realizes the ratio

E PFVPBF, well a. + E a, + F + F + BF + BPF. (14)

The function of the switch 8 is that the higher bits (g6, g,) of g are fed to the input of the decoder 28, and the lower bits (gi, gi, go) "and the input of the decoder 29. At the outputs of these decoders, 16 - bit word c (c, c ,, ..., c ij) with one unit and 8-bit word P (Rd, P (, ..., P) with one unit. The words sire go to block 30, where a 15-bit is formed

binary word t (tj) and

12-bit binary word g (gi g, 2) If equation (3) has no solutions (), then all the bits of the words t and q are equal to one. If equation (3) has a solution (), then one bit in each of the words t, q can be equal to zero. The bit tj is equal to zero, if the highest bits (x, Hu, x, Xs) of the solution form the number j. There are exactly four such cases, since all 63 solutions of equation (3) are different. In order to create a bit t-in b 30, a logical AND-OR-NOT type of function is implemented ..Pj7V jeVC5, Pje and to form a discharge q g - type futsi, VC ,,,, P, VC, 3P, Words t and q from block 30 enters block 31, where the final combining of signals is performed with the help of AND-NES elements, and times Xg are formed. In this case, realizations of the X range are the expressions (q q q q gyqio figf 7) Xj t, tjtjt tg t, t tjj. ; 6 7 X t, t, t 4 u with LL, L, - 14 - / 5 -9 (0 - fl -I (E AND t (y 6 t, In the decoder 32, the expression D XjVx2V, .. VXg. Functions , performed by the multiplier 6, are similar to the functions performed by the driver 12 and the adder 13. In block 7, the values of F / s, eVS, V .., VS, oH F2 Sj6VS 5V .., VSyp are formed in accordance with expression (7) In the OR element 44, the value of VF2 is formed, a signal is generated at the output 19. In the case of K, the device operates in the same way, and the discharge locators are elements of the GF field (2), system (2) and equation (3) are solved by the GF (2) field, all decoding operations are performed in the field GF (), where, nt, n K + 2m + 1. In other words, the field GF (2) is replaced by the field GF (), for example, if K 128, then all operations during operation of the device are performed in field GF (2).

fig.Z

fpui i

Claims (5)

1. DEVICE FOR CODE DECODING, containing the first and second adders, an oddity calculator, a decoding rejection unit, a multiplier, a code generator, an corrector, an error detection unit and a first adder block, one of which is combined with the first input of the parity calculator, information input of the corrector and connected to the first input of the device, and the first output is connected to the first inputs of the error detection unit, the code generator and the first adder, the second input of the parity calculator is connected to the second input of the device, and the output is with the first input of the decoding reject block, the first output of the corrector is the first output of the device, the output of the decoding reject block is the second output of the device, the output of the first adder is connected to the first correcting input of the corrector, the second correcting input of which is connected to the output of the second adder, to the input of which I connect -Chen the output of the code generator, the output of the error detection unit is connected to the second input of the reject decoding unit and is the third output of the device, characterized in that In order to increase the speed and reliability of the processed information, the second and third adder blocks, an inverse root calculator, an excluded code generator and a parity corrector are introduced into it, the first input of which is combined with the second input of the device, the second input is combined with the second input of the error detection unit and connected to the output of the parity computer, the third input is connected to the output of the block § £ Λ "** error detection, the fourth input with the output of the decoding reject block, and the output is the fourth output of the device, the first input of the second adder block is combined with the inputs of the first and third adder blocks, the second input is connected to the second output of the first adder block, and the output is with the first input of the multiplier and the second input of the code generator, the output of the third adder block is connected to the third input of the error detection unit and the second input of the multiplier, the third input of which is connected to the first output of the first adder block ditch, and the output is to the input of the reciprocal root computer, the first output of which is connected to the third input of the code generator, the output of which is connected to the second input of the first adder, the second output of the reciprocal root computer is connected to the third input of the decoding rejection block, the fourth input of which is connected to the output excluded code generator, first input to 1190525 is connected to the output of the first adder, the second input to the output of the second adder, and the third input to the second output of the corrector, the control input of which is connected to the output of the error detection unit, the output of the multiplier is connected to the fifth input of the decoding rejection unit. 2. The device according to claim 1, characterized in that the corrector contains a block of AND-OR-NOT elements, an adder, a block of inverters, first and second decoders of the upper bits, the first and second decoders of the lower bits, the control inputs of which are combined and connected to the control input of the corrector, the first correcting input of which is connected to the information inputs of the first low and high decryptors, and the second correcting input - with the information inputs of the second low and high decryptors, the outputs of the black decoders block of AND-OR-NO elements are connected to a first input of an adder, whose second input is connected through inverter unit to an information input of the corrector, and the output - to the first output of the corrector, the outputs of decoders coupled to the second output of the corrector. 3. The device according to paragraphs. 1 and 2, characterized in that the inverse root computer contains junior and senior bit decoders, a block of AND-OR-NOT elements, a block of AND-NOT elements and a zero decoder, the input of which is connected to the output of the block of AND-NOT elements and the first output of the inverse calculator roots, the input of which is connected to the inputs of the decoders of the lower and senior bits, the outputs of which are connected with the corresponding 1190525 the current inputs of the block of elements ·. AND-OR-NOT, the output of which is connected to the input of the block of AND-NOT elements, the output of the zero decoder is connected to the second output of the inverse root computer. 4. The device according to paragraphs. 1-3, characterized in that the generator excluded codes contains the first, second, third and fourth elements AND and the first and second elements OR, the inputs of the first and second elements AND are connected respectively to the first and second inputs of the generator excluded codes, and the outputs with the first inputs respectively, of the first and second elements OR, the second inputs of which, as well as the first and second inputs of the third and fourth elements AND are connected to the third input of the shaper excluded codes, the outputs of the third and fourth elements AND are connected to imi inputs of the first and second OR elements, outputs of which are connected to the negative output of the codes. 5. The device according to paragraphs. 1-4, wherein the parity corrector contains the first and second elements And and an adder, the first input of which is connected to the first input of the parity corrector, the second input of which is connected to the first input of the first element And, the third and fourth inputs of the corrector parities are connected to the corresponding inputs of the second element And, the output of which is connected to the second input of the first element And, the outputs of the elements And and the second and third inputs of the parity corrector are connected to the corresponding second inputs of the adder.