SU1185284A1 - Shaper of codes of p-sweep for plan position indicator - Google Patents

Abstract

FORMER OF CODES OF A RADIAL-CIRCULAR SCAN FOR A CIRCLE REVIEW INDICATOR of the author. St. 1a30751, characterized in that, s. In order to reduce distortions in the displayed information, two switch codes are entered into it, the information inputs of which are connected to the corresponding outputs of the first and second memory blocks, the control inputs to the trigger output, and the outputs to the corresponding information inputs of the first and second accumulating adders.

Description

I

The invention relates to radio engineering and can be used in round-up indicators.

The purpose of the invention is to reduce the amount of information displayed.

FIG. 1 is provided with a structural electrical circuit of the proposed driver; FIG. 2 is a structural electrical accumulator circuit of FIG. 3 linear sawtooth sweep voltage with a compensating loss in the deflection system of the additive (pedestal); in fig. 4 Structural electrical circuit of the commutator of codes and signal conditioner linearity.

The shaper contains the sensor 1 of the antenna angle code, the element HE 2, the decoder 3 signs of the cosine of the angle, the blocks 4 and 5 of the controlled inverters, the blocks 6 and 7 of the memory accumulating accumulators 8 and 9, the generator 10 clock pulses, element 11, the counter 12, trigger 13 and switches 14 and 15 codes.

The shaper works as follows.

Sensor 1 receives the p-bit binary code of the antenna position angle. Discharges from the first. the (p-2) -th codes go to blocks 4 and 5 of the controlled inverters, which are controlled by the direct or inverted (p-1) -th code bit. The highest n-th bit of the antenna angle code is a sign and is used as a sinoi sign. To determine the sign of ccs.oi, the device uses a 3-digit cosine decoder, the input of which receives two high-order bits of the antenna angle angle code. The decoder is built on chips and contains two NOT elements, two AND elements and an OR element. The values of the cosine sign depending on the value of the signals at the input of the decoder are given in the table.

185284

The table shows that the cose / sign

ABOUT

takes value

in the first and

II 4 It

fourth quadrants and level. 1 in the second and third quadrants. The block of controlled inverters serves to generate a direct or inverted value of the antenna angle angle code from 0 to 90, which ensures the formation of the sinotCcosflt code) at the outputs of memory blocks 6 and 7 ranging from 0 to 180 °. The bits of the antenna angle code from the first to (n-2) -th are fed to the first inputs of the elements of the blocks 4

and 5 controlled inverters, the second inputs of which receive (n-1) -th bit or its inverted value, respectively. The inversion of the (p-1) -th bit is performed by the HE-2 element.

The blocks of controlled inverters operate according to the following logic.

Signal 1 arriving at one input of the element inverts the signal

coming to another entrance. If the signal O is received at one input, then the value of the signal at the other input passes to the output of the element without changing the level. In accordance with

By this, the O in (p-1) -th code bit coming from the output of sensor 1 to block 4 passes the direct antenna position angle code to the address inputs of memory block 6, and the control signal from the output of the HE element 2 produces the reverse angle code at the inputs of the memory block 7.

When the angle of rotation of the antenna is in the second or fourth

the quadrant, the (n-1) -th digit of the code takes the value 1 and the reverse angle code arrives at the address inputs of memory 6, and the forward position angle code arrives at the inputs of memory 7

antennas. Memory block 6 provides storage for the sine codes, and memory block 7 provides the cosine codes of the angles from 0 to 90. Upon receipt at the address inputs of blocks 6 and 7 of the memory of codes in

In accordance with the angle of rotation of the antenna, a sine code is generated at the output of block 6, and a cosine code at the output of block 7. These codes are fed to the corresponding inputs of accumulating adders 8 and 9 (FIG. 2) and switches of codes 14 and 15 (FIG. 4).

Accumulating adders 8 and 9 A series of elementary increments of coordinate values obtained from blocks 6 and 7 of the memory of sinot, cosois, are used to convert the cathode ray tube (CRT) beam along the CRT radius during the sweep. The switches of codes 14 and 15 are designed to shift the bits and switch the sine (cosine) codes from the outputs of memory blocks 6 and 7 relative to the second information inputs of accumulating adders 8 and 9 to the formation time of the radial sweep. Thus, the codig switch is changed by the weight additive (pedestal) (Fig. 3) to the codes obtained on the accumulating adder. At the same time, the pedestal addition code does not accumulate, but only stacks with each; the result of accumulation at the output of the adder. The signal from the trigger includes this code actually at the time of formation of the pedestal. In order to generate the radial-sweep codes, the device also contains a generator of 10 clock pulses, element 11, and counter 1. trigger 13 (Fig. 1). The frequency f of generator 10 is determined by the ratio m inic (% where c is the velocity of propagation of electromagnetic waves in the air; mdx is the maximum display distance on the screen of the circular view indicator; Jpai is the sweep duration; is the number of elements on the scan radius (k is the counter size 12 , is selected on the basis of various factors: resolution of the CRT ability, the diameter of the electron spot, the diameter of the CRT The trigger pulse arrives at the synchronizing trigger input 13 and sets it to one state. The trigger output signal Parallel 13 allows clock pulses from generator 10 to pass through element I 11 to counting inputs of counter 1 2 and accumulating adders 8 and 9. Binary counter 12 provides counting of pulses during the sweep duration. From the outputs of blocks 6 and 7 of memory, the values of sino and coso is fed to the inputs of the lower bits of the accumulating adders 8 and 9, and the ac outputs of the switches 14 and 15 codes to the inputs of the higher bits of the accumulating adders 8 and 9. With each impulse of the radial sweep, the transducer. from the output of the And 11 element, the sine (cosine) codes are summed with the codes accumulated in the registers in the process of the arrival of the preceding pulses. The transfer pulses from the lower to the higher bits provide the formation of radial codes. In the higher bits, these codes are summed with the codes from codes switches 14 and 15, thus generating codes at the output of the driver. The overflow pulse of counter 12 is the pulse of the end of the display of the maximum sweep range and zeroes the registers of accumulating adders 8 and 9. The signal from the output of counter 12 also enters the trigger input 13 and sets it to zero. Clock pulses from the generator 10 to the counting inputs of the counter 12 and accumulating adders 8 and 9 are not received. With the arrival of the next start pulse, the cycle of generating the radial-sweep codes is repeated. Thus, a change in the coding at the outputs of the accumulating adders and 9 provides a radially circular sweep of the CRT beam and compensation for active losses in the deflecting system of the circular view indicator, which displays information at small distances. In this case, the most significant bit of the code of the angle of position of the antenna and the decoder of the cosine sign determine the polarity of the sweep voltages. .- The introduction of switches 14 and 15 codes allows to obtain a constant additive in the values of the radial components of the sweep proportional to the current value of the sine or cosine code, and the value of this additive can be changed, shift codes (switch) in the switches of codes resisted the signal to the Linearity. The additive is formed only during the formation of the radial sweep code, and at the maximum amplitude of the sweep voltage, and therefore at the maximum losses in the deflection system, the maximum additive is also obtained to compensate for these losses.

In position 1, switch B1, as shown in FIG. 4, the pedestal code from the output of the memory unit 6 (7) is transmitted to the second information inputs of the accumulating adder 10

 (11) without shift. In position

2.3 .... switch B1, the pedestal code is shifted towards the lower bits, and the voltage amplitude of the pedestal is reduced by 2, 4, 8, 16, etc. times, while the leading free bits add up zeros.

JfuHtuaoe / rrb and MT. launch j / fff / f siff d

B

.s

Yu

Bj

 P

FIG. g flip-flop fS 81 / gimvimost IP Sinfcos) 2p uinfco) 3/7 Sin (COS) ffnl) p sift (cos fT7p 3i./7fcOS) 2p) Er sLfffcffs) p uLnfcou) g mp sifjfcos) / 2) fl) ( frtt) p SLfffcOs) mp ifjfco) ffn-fjp QifffCifS Fie. ZP u

Claims (1)

CIRCUIT RADIAL CODE FORMER FOR INDICATOR CIRCLE REVIEW by ed. St. No. 1030751, characterized in that, with. In order to reduce distortions of the displayed information, two code switchers are introduced into it, the information inputs of which are connected to the corresponding outputs of the first and second memory blocks, the control inputs are connected to the trigger output, and the outputs are connected to the corresponding information inputs of the first and second accumulating adders. 1 185284