SU1184097A1 - Adaptive number-to-time interval converter - Google Patents

Description

The invention relates to radar systems and radio navigation and can be. Used in systems with a time-pulse presentation of information in which information

tive parameter is the time interval between the pulse signals. ·

The aim of the invention is to improve the accuracy of the converter code - ’θ time interval by reducing the influence of the instability of the clock frequency.

FIG. 1 shows the structural 15 scheme of the adaptive transducer code - time interval; in fig. 2 block diagram of the code converter; in fig. 3 - structural diagram

control unit; in fig. 4 shows an example of execution of a comparison unit.

The converter contains a clock “generator 1, logical block 2,

made on the trigger and the element And, the input bus 3, the counter 4 pulses, block 5 comparison, the output bus 6 of the Converter 7 code, the output bus 8 of the storage register 9, the first input 10 of the Converter 7 code, the output bus 1 1.

The code converter 7 comprises a reference generator 12, a reference time generator 13, a frequency divider 14, a frequency reference value sensor 15, a pulse counter 16, a trigger 17, the first coincidence element 18, block 19

3 1

control, the second element 20 matches, a unit 21 controlled inverters with outputs 22, a register 23 with outputs 24, a switch 25 with outputs 26 and 27, a first comparison unit 28 with outputs 29, a persistent storage device 30, an arithmetic logic unit 31 with outputs 32 , the sensor 33 permissible deviations with the outputs 34, the second block 35 comparison, the second input 36.

The control unit 19 contains 0-flip-flops 37 and 38, an input 39 for connecting the control unit 19 to the output of the driver 13 of the reference time intervals, waiting for multivibrators 40-42, an inverter 43.

Block 5 comparison contains four-digit elements 44-46 comparison codes, the element AND NOT 47, input 48 and the additional input 49.

The output of the clock generator 1 is connected to the first input of the logic unit 2, the second input of which is the input bus 3, and the output is connected to the input of the counter 4, the outputs of which are connected to the corresponding first inputs of the block 5 whose output is the output bus 11, the first input of the converter 7 is combined with the second input of block 5 and connected to the output of the clock generator 1, the second input is connected to the output of block 5, the outputs to the corresponding third inputs of block 5, and the third inputs to the corresponding outputs of the memory register 9.

The input of the shaper 13 of the Converter 7 is connected to the output of the reference generator 12, and the output - with. the first inputs of block 19, trigger 17 and divider 14, the second input of which is the first input of converter 7, the second input of which is the second input of block 19, the third inputs are connected to the corresponding first address inputs of permanent memory 30, the outputs of which are the corresponding outputs 6 of converter 7, and the second address inputs are combined with the corresponding first inputs of the switch 25 and block 28 and are connected to the corresponding first outputs of the register 23, the second output of which is connected to the control them

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the input of the persistent storage device 30, and the first inputs are combined with the corresponding second inputs of the switch 25 and 5 of the block 28 and connected to the corresponding outputs of the block 21, the first input of which is combined with the first input of the element 18 and the second input of the register 23 and connected to the output 10 of the trigger 17, the second input of which is connected to the first output of the counter 16, the second inputs of which are combined with the corresponding first outputs of the divider 14 and connected 15 to the corresponding second inputs of the block 21, the first input is connected to the second output of the divider 14, the second inputs with the corresponding outputs of the sensor 15, and the third input 20 is combined with the third input of the divider 14 and connected to the output of the element 18, the second input of which is connected to the first output of the block 19, the second output of which is connected to the 25 fourth inputs of the divider 14 and

counter 16 and the third input of the trigger 17, and the third output is connected to the first input element 20, the output. which is connected to the third input of the register 23, and the second input - to the output of block 35, the inputs of which are respectively connected to the outputs of the sensor 33 and the arithmetic logic unit 31, the inputs of which are respectively connected to the outputs of the switch 25, the third inputs of which are connected to the corresponding outputs of the block 28 .

The input of the inverter 48 of the block 19 is the first input of the block 19 and the output is connected to the C-input of the first E-flip-flop 37, the 37-input of which is a potential-free bus, the 5-input is combined with the first inputs of the waiting multivibrators 40-42 and is connected to the output the second три-flip-flop 38, and the O-input of the second три-flip-flop 38 is combined with the second inputs of the waiting multivibrators 40-42 and is a zero potential bus, and the second input of the block 19 is the third input of the first waiting multivibrator 40, the output of which is the first output of the block 19 and connected to 55 mp tim input of the second monostable multivibrator 41 whose output is connected to a third input of the third monostable multivibrator 42, vy40

45

50

five

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the stroke of which is connected to the C-knob of the second три-flip-flop 38 and is the second output of block 19, the third input of which is the output of the second waiting multivibrator 41.

Converter code-time interval works as follows.

In the initial state, the logic unit 2 is closed and the pulses of the clock generator 1 are not fed to the input of the counter 4, which is set to the initial zero state, the output signal of the comparing unit 5 is absent due to the mismatch between the codes of the counter 4 and the converter 7 of the code that generates the code in with the frequency of .actual generator 1 and the code coming from the storage register 9, in which the source code is entered.

After the first operation of the control unit 19, its output signals lead to the corresponding state, when switched on in an arbitrary state, the circuit elements of the code converter 7, i.e. the divider 14 is reset to the zero state, the code from the source value sensor 15 is written to the counter 16, the trigger 17 is set to the zero state corresponding to the first input of the first coincidence element 18, the code from the output of the controlled inverter unit 21 is entered into the register 23.

In the initial state, the ϋ-trigger 37 is set to one and does not affect the ϋ-'trigger 38, which is in the zero state, the output signal from the output of the □ trigger 38 prohibits the launch of multivibrators 40-42.

The output code of the register 23 via the bus 24 is fed to the second address inputs of the persistent storage device 30, the first address inputs of which receive the code from the storage register 9.

In accordance with the address code at the input of the persistent storage device 30, the required converter code 7 is output at its output (taking into account the correction).

When a start pulse arrives at the input of logic unit 2, the input bus 3 arrives at the input of counter 4 pulses from the output of the clock generator 1. When the binary counter 4 reaches the state that matches the output code of the converter 7 code, the comparison unit 5 forms an output signal on the output bus 11.

The output signal of the adaptive converter code is the time interval from the output bus 11 to the second input 36 of the converter 7 of the code, and therefore to the input of the first multivibrator 40. The starting resolution of the multivibrator 4042 occurs after the formation of the output signal of the former 13 reference time intervals, while ϋ- the trigger 37 by the signal from the output of the inverter 43 is set to the zero state. the time of the end of the formation of the reference time interval. Next, the signal from the output of the trigger 37, the trigger 38 is set in the state when the output signal of the trigger 38 enables the multivibrators 40-42 and resets the trigger 37 to its original state. The output pulses of the multivibrators 40-42 sequentially set the circuit elements to the initial state, including the last pulse 0-trigger 38 is allowed to the initial state.

If the codes at the inputs 48 and the outputs 6 do not match, the element 47 (FIG. 4) is closed by the output signal of the code comparison element 44. When coinciding .codes at the outputs of the elements 44-46 comparison codes appear signals with the level of logical units, which are input to the equality of the lower bits.

When the codes completely coincide, the output signal of the element 44 opens the input element 47 and when the next clock pulse arrives at the additional input 49 of the comparator unit 5, an output pulse appears on the output bus 11. As a result of strobe pulses of the clock generator 1 through the additional input 49, a delay is added to be formed is a constant value determined by the delay element 47.

7

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Converter 7 code works as follows.

The input of the driver of the reference interval 13 from the output of the reference generator 12 continuously receives pulses of a stable repetition frequency, and at the output of the former 13 pulses of the required duration T with a period of 2T are formed. During the time T within the duration of the output pulse of the driver 13, which is fed to the input of the frequency divider 14, in the latter there is a division of the pulse repetition frequency of the generator 1, fed through the bus 10. The output pulses of the frequency divider 14 are fed to the input of the counter 16, in which The code of the number corresponding to the nominal frequency of the clock generator 1 is preliminarily entered in the counter 16 at the end of the interval T the number is recorded

Ch ^ (th), <’>

where N is the number in the counter 16;

K - division ratio of the frequency divider 14;

P - the number of digits of the counter 16; . M - the number corresponding to the nominal frequency of the clock generator 1;

ί - oscillation frequency of the clock generator 1.

The oscillation frequency of the clock generator 1 can be expressed by the formula

£ = · · _ο (? ^Ν ^?

(2)

where ί _θ is the nominal frequency of clock generator 1;

o is the relative deviation of the frequency of the clock generator 1 with respect to 1 _o .

The parameters of the driver 13, the divider 14, the sensor 15, the counter 16 are selected from the condition

D

4 ⁴ o = ^g "- ^m · ^(g)

Taking into account formula (3), expression (1) can be written in. the form

»4 £ l.

 (From formula (4) it can be seen that the readings of counter 16 are directly proportional to the relative frequency deviation of the clock generator 1. The weight of one pulse at the input of the counter ”16 from formula (4) is

'' ΪΤ ' ⁽⁵⁾

to ^1o

where L is the weight of one pulse at the input of the counter 16.

Example. Calculate the parameters of the Converter 7 code using the above formulas. Suppose you want to ensure that the low-order weight of counter 16 is equal to 8 ^ 5 · 10 ~ ⁶ at the nominal value of the frequency of the clock generator 14992500 Hz. Set the time T = 1 s and from the formula (5) find the value of K = 74.9625. Round K to an integer value K = 75. Set the number of digits of the counter, equal to 18, which corresponds to the capacity of the counter 262144. From the formula (3) determine the number M = 62244. Specify the value of 5 ^ by the formula (5):

5, -5.002501 · Ι0 ' ⁶ , _g .

(6)

The counter 16 in the case of exceeding the oscillation frequency of the clock generator 1 nominal frequency is full after rendering the number of pulses corresponding to the nominal frequency. For the considered example, the number of pulses at the input of the counter 16 before overflow is 199900. After the counter 16 overflows (within the pulse with duration T), the output of the trigger 17 receives a logic level zero, which closes the first coincidence element 18, and the controlled inverter unit 21 is set to transfer direct code. With the advent of a voltage drop corresponding to the end of the pulse at the output of the driver 13, to the input of block 19, the latter allows the launch of the first multi

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vibrator 40 (starting occurs with the arrival of a pulse from the output bus 11), the output pulse of which is fed to the input of the first coincidence element 18 and starts the second multivibrator 41 of the block 19. Similarly, the pulse from the output of the second multivibrator of the block 19 enters the input of the second coincidence element 20 and starts the third multivibrator 42 of block 19, which generates the third pulse at the output of block 19, which is fed to the inputs for setting the initial state of the divider 14 of the counter frequency 16 and the trigger 17.

Since the launch of the first of three serially connected multivibrators 40-42 is performed by a pulse corresponding to the end of the device operation cycle, the output pulses of the indicated multivibrators turn out to be coherent with the moment the formation of the time interval ends (they are outside the ·· form of the time interval).

If there is a enable signal at the second input of the second element 20, the second pulse of the block 19 records the output code of the controlled inverters 21 into the register 23. In the case of decreasing the frequency of the clock generator 1 with respect to the nominal value, the first coincidence element 18 remains open and the first pulse c the output of the first stage of the block 19 passes to the output of the element 18 and, having entered the subtractive inputs of the frequency divider 14 and the counter 16, is subtracted from the contents of the indicated counters by one unit of the lower order. The output of the frequency divider 14 is connected to the summing input of the counter 16, so in the subtraction mode, the frequency divider 14 and the counter 16 operate independently of one another. The subtraction operation is performed to convert the counter code 16 into the reverse one, taking into account the symmetry relative to the zero state of counter 16, and the output of the unit 21 controlled inverters forms the code of the absolute deviation from the nominal frequency of the clock generator 1. For example, in counter 16, one

The unit of the least significant digit is displayed by the code ... 0001 (the least significant digit on the right), while decreasing the frequency by one unit in the counter 16 is displayed by the code ... 1111 (the lower order digit on the right).

After subtracting the low-order unit and inverting the code in block 21 of the controlled inverters (for the case of decreasing the frequency by one unit in the counter 16), the output of the block 21 of the controlled inverters forms the code ... 0001 (the low-order bit to the right), i.e. the same code as for the case of exceeding the nominal frequency. Converting the counter code 16 makes it possible to reduce by 2 times the required amount of permanent memory 30 for the case of the symmetric distribution of the probable frequency deviations of the clock generator 1 relative to the nominal value. The output code of the register 23 displays the frequency deviation of the clock generator 1 available for these operating conditions and, arriving at the second address inputs of the persistent storage device 30, selects a part of the device 30. The specific code of the number at the output of the device 30 is output based on the code from the storage register 9 arriving to the outputs 8. Similarly, the control signal from the output of the trigger 17 in the device 30 switches from an array of values for positive values of deviations to an array for negative values from clock frequency clone 1. In this case, the low-order bit of the register stores information on the status of the trigger 17, which corresponds to the moment of recording in the register 23 information from the output of the block 21 controlled inverters. . The low-order output signal of the register 23 directly controls the permanent storage device 30 on the control input. In this case, half of the microcircuits included in the device 30 through the inputs “Sampling of microcircuits” are connected directly to the low-order output of the register 23, and the other half through an inverter included in the device 30.

eleven

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To eliminate the influence of oscillations of the output code of the counter 16, due to the discrete principle of operation, using the switch 25, the first comparison unit 28, the arithmetic logic unit 31, the tolerance sensor 33, the second comparison unit 35, an algorithm for recording the code in the register 23 but condition of significant code changes. If we designate the numbers stored in register 23 and received at its input via bus 22, A and B, respectively, and the numbers at the outputs of the arithmetic logic unit 31 and sensor 33, respectively, C and B, then the algorithm for writing a number to register 23 can be written following expressions:

Αί? Β, C = A - B; (7)

A B, C = B - A; (eight)

C> B (record allowed)

C ^ B (no entry allowed).

B depending on which of the numbers A and B is greater by. the absolute value, on the bus 23 from the first comparison unit 28, the corresponding command is issued for the switch 25. The result of calculating the difference between the numbers A and B is output from the device 31 via the bus 32 to the second comparison unit 35, the second input of which receives the number code from the tolerance sensor 33 . When the number C is more than the allowable output from the tolerance sensor 33, a resolution signal is output at the output of the second device of the block 35, which opens the second coincidence element 20, and the new frequency deviation code is recorded with the output pulse of the last one.

Thus, with insignificant fluctuations of the number in the counter 16 relative to the number in the register 23, the number in the register 23 remains unchanged, which ensures that the code at the output of the code converter (permanent storage device 30) remains unchanged.

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FIG

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Fig 3

Fig.k

Claims (3)

1. ADAPTIVE TRANSMITER CODE - INTERVAL TIME, containing a memory register and a clock generator, the output of which is connected to the first input of the logic unit, the second input of which is an input bus, and the output is connected to the input of a pulse counter, the outputs of which are connected to the corresponding first inputs of the comparison unit, the output of which is an output bus, characterized in that, in order to improve the accuracy of the converter, a code converter is entered into it, the first input of which is combined with the second input of the comparison unit connected to the output of the clock generator, a second input connected to the output of the comparator unit, outputs - to the corresponding inputs of the third comparator unit, and the third input - to the corresponding outputs of the memory register. 2. The converter according to claim 1, characterized in that the code converter is made on the reference generator, frequency divider, frequency reference value sensor, pulse counter, trigger, first and second match elements, control unit, controlled inverter unit, register, switch, first and the second unit of comparison, a persistent storage device, an arithmetic logic unit, a tolerance sensor and a driver for the reference time interval, the input of which is connected to the output of the reference generator and the output from the first and the inputs of the control unit, the trigger and the frequency divider, the second input of which is the first input of the code converter, the second input, which is the second input of the control unit, and the third inputs are connected to the corresponding first address inputs of the permanent storage device, the outputs of which are the corresponding outputs of the code converter, and the second address inputs are combined with the corresponding first inputs of the switch and the first comparison unit and connected to the corresponding first register outputs, the second The output of which is connected to the control input of the persistent storage device, and the first inputs are combined with the corresponding second inputs of the switch and the first comparison unit and connected to the corresponding outputs of the controlled inverter unit, the first input of which is combined with the first input of the first matching element and the second register input and connected to trigger output, the second input of which is connected to the first output of the pulse counter, the second outputs of which are 1184097 connected to the corresponding second inputs of the controlled inverter unit, the first input is connected to the second output of the frequency divider, the second inputs are connected to the corresponding outputs of the frequency reference sensor, and the third input is connected to the third input of the frequency divider and connected to the output of the first coincidence element, the second input of which is connected to the first output of the control unit, the second output of which is connected to the fourth inputs of the frequency divider and pulse counter and mp The third trigger input and the third output are connected to the first input of the second coincidence element, the output of which is connected to the third register input, and the second input to the output of the second comparator, whose inputs are respectively connected to the outputs of the tolerance sensor and the arithmetic logic unit, whose inputs respectively connected to the outputs of the switch, the third inputs of which are connected to the corresponding outputs of the first unit of comparison. 3. The converter according to claim 2, in that the control unit is made on two три-triggers, three waiting multivibrators and an inverter, whose input is the first input of the control unit, and the output is connected to the C-input of the first-trigger. The Ώ-input of which is a zero potential bus, the 8-input is combined with the first inputs of the waiting multivibrators and connected to the output of the second 1) -trigger, and the output is connected to the 8-input of the second Ώ-trigger, while the C-input of the second ϋ-trigger combined with the second inputs of the waiting multivibrators and is a bus well the second input of the control unit is the third input of the first standby multivibrator, the output of which is the first output of the control unit and connected to the third input of the second standby multivibrator, the output of which is connected to the third input of the third standby multivibrator, the output of which is connected to the C input of the second C -trigger. and is the second output of the control unit, the third output of which is the output ^ of the second standby multivibrator.