SU1174869A1 - Peak detector - Google Patents

Abstract

1. A PEAK DETECTOR containing the first analog 1st switch, resistor, voltage follower, whose input is connected via a parallel-connected storage capacitor and the second analog switch to the detector common bus, the control input of the second analog switch forms Input Reset detector, and a comparator, which is distinguished by the fact that, in order to expand its functionality, an inverter and a digital switch are inserted in it, the input of the first analog switch being connected to the detector input, and the black output A resistor with a voltage repeater input, a non-inverting comparator input is connected to the detector input, an inverting input to the detector output, and an output to the first input of the digital switch directly and to the second input through the inverter, the control input of the digital switch forms the Floor input detector, and the output is connected to the control input of the first analog switch. 2. The device according to claim 1, which means that the digital switch with S switch is made on three AND-NOT elements and an inverter, the first input (the L digital input of the digital switch is connected to the first input of the first one from the NAND element, output which is connected to the first input of the second element, the output of which is connected to the output of the digital switch, the second input of the first element AND-NOT is connected to the control input of the digital switch and the input of the inverter, the stroke of which is connected to the second input 4; sk of the third element AND-NOT, the first input 00 Gb which is connected to in orym input of the digital switch, and an output to a second input of the second AND-NO element.

Description

This invention relates to electrical measuring technology. The purpose of the invention is the extension of functionality due to the possibility of converting the NIN signals of both polarities,. Figure 1 shows a block diagram of a peak detector; Fig. 2 shows an example of a digital switch. The peak detector contains the first analog switch 1, whose input is connected to the detector, and the output through 2 to the input of the voltage follower 3, the input of the repeater 3 through the memory capacitor 4 connected in parallel and the second analog switch 5 connected to the common bus of the detector, and the output is to the detector output and to the inverting input of the comparator 6, the non-inverting input of which is connected to the detector input, and the output to the input of the inverter 7, and digital switch 8, the first input 9 of the switch 8 is connected to the output of the comparator 6, the second input 10 to the output Inverter 7, output 11 to control input of switch 1, control input I2 to control input Polarity of detector, control input of switch 5 is connected to control input Reset detector. Voltage repeater 3 is an operational amplifier covered by 100% negative voltage feedback. Digital switch 8 contains the first logical element IS-NOT 13, the first input of which is connected to input 9, the second input - to INPUT 12, and the output - to the first input of the second logical element AND-HE 14, the output of which is connected to output 11 and the second input is to the output of the third logical element AND-NOT 15, the first input of the element AND-NOT 15 is connected to the input 10, the second input to the output of the inverter 16, the input of which is connected to the input 12 of the switch. The device works as follows. Before each measurement starts, a logical 1 signal is sent to the Reset for a time sufficient to fully discharge the storage capacitor 4. The second analog switch 5, closes, discharges the capacitor 4. The logical incoming signal is fed to the input polarity. to the input 12 of the control of the digital switch 8. In this case, the signal at the output 11 of the digital switch 8 corresponds to the signal at its first input 9. When a positive polarity signal appears at the input of the device The digital input of the comparator 6 exceeds the potential of its inverse input, close to zero, because the capacitor 4 is discharged. In this case, at the output of the comparator 6, a signal of logical 1 is generated, the inputs through the digital switch; the transmitter 8 is connected to the control input of the first analog switch 1, which is closed. Through the resistor 2, the charge current of the capacitor 4 begins to flow. After reaching the peak value of the input signal, the potential of the direct input of the comparator 6 becomes lower than the potential of its inverse input. In this case, the output of the comparator 6, and therefore the logical input O, is set at the control input of the first analogue cable 1. The key 1 is opened, and the storage capacitor 4 stores the peak value of the measured positive signal received through the voltage follower 3 at the detector output . Comparator 6 is held in the state of logical O until the measured signal exceeds the voltage values of the capacitor 4. The device operates in measuring the peaks of the negative signal as follows. The polarity signal is fed to the input of a logic signal O, which is fed to the input 12 of the control of the digital switch 8. At the same time, the signal at the output of the 11-digit switch 8 corresponds to the signal at its second input 10. After applying the corresponding signal to the input Reset, the storage capacitor 2 is discharged. When a negative polarity signal appears at the device input, the potential of the inverse input of the comparator 6, which is close to zero, exceeds the potential of its direct input. At the output of the comparator 6, the logical O signal is fixed, and at the output of the inverter 7 and the second input 10

 eleven

The switch 8 appears as a logical signal 1. The same signal enters the control input of the first analog switch 1 and closes it. Through the resistor 2, the charge current of the capacitor A begins to flow. After reaching the peak value of the input-negative signal, the potential of the inverse of the input of the comparator 3 becomes lower than the potential of its direct input, which leads to

748694

logical O on the control input of the first analog key 1 and its opening. The memory capacitor 4 stores a peak value 5 of the negative input signal, which is fed through the voltage follower 3 to the detector output. Comparator 6 is held in the logical state O until the input negative

10 good signal will not be less than the voltage on the storage capacitor

K12

.2

Claims (2)

1. A PEAK DETECTOR containing a first analog switch, a resistor, a voltage follower, the input of which is connected to the detector’s common bus through a parallel connected storage capacitor and a second analog switch, and the output is connected to the detector’s output, the control input of the second analog switch forms the Reset ”input of the detector, and a comparator, characterized in that, in order to expand the functionality, an inverter and a digital switch are introduced into it, and the input of the first analog key is connected to the input of the detector, and the output through side - with the input of the voltage follower, the non-inverting input of the comparator is connected to the input of the detector, the inverting input is connected to the output of the detector, 'and the output is connected to the first input of the digital switch directly and to the second input through the inverter, the control input of the digital switch forms the input Polarity of the detector, and the output is connected to the 'control input of the first analog key. 2. The device according to π.1, characterized in that the digital switch is made up of three AND — NOT elements and an inverter, the first input of the digital switch being connected to the first input of the first AND — NOT element, the output of which is <? connected to the first input of the second AND-NOT element, the output of which is connected to the output of the digital switch, the second input of the first AND-NOT element is connected to the control input of the digital switch and the inverter input, the output of which is connected to the second input of the third AND-NOT element the input of which is connected to the second input of the digital switch, and the output to the second input of the second element AND NOT. QO Oft ζ ©