SU1173408A1 - Device for determining maximum out of binary numbers - Google Patents

Abstract

A DEVICE FOR DETERMINING .MAXIMAL FROM rm BINARY NUMBERS, containing yy groups of elements AND by n-1 elements AND in each group, where n is the number of digits of the numbers being compared, -tn groups of memory elements by n memory elements in each group, n multiple input elements OR analysis of bits, m elements OR zeroing, control elements AND, result register, and the direct output of each i-th memory element of the group, where i 1,2, ..., r, k 1,2, ...., m is connected to the k-th input of the i-ro of the lightest bit analysis element, the output of which is connected to the first input of the .i-ro control About And, whose output is connected to the installation input to the i-ro unit of the result register, the output j-ro of the I control element, where j 1,2, ..., ri-1 is connected to the first inputs of the ix elements And all the groups, the second input of the j-ro, the AND element of the 1st group is connected to the inverse output of the j-ro memory element of the k-th group, the output (nl) -ro of the AND element of the group is connected to the first input of the k-ro element OR zeroing The output of which is connected to the setup input to the zero state of the h-ro memory element of the k-th group, characterized in that, in order to improve speed , n-1 elements And reset, n-2 elements and analysis of bits, a multi-input element And and a pulse generator, the start input of which is connected to the start input of the device, and the output connected to the second inputs of all control elements And the control input of the multi-input element AND and the inverse inputs of all i elements of the zeroing, the direct input of the j-ro element and the zeroing are connected (L to the output of the j-ro bit of the output register, and the output is connected to the first inputs of the installation to zero state JX memory elements of all groups , the second inputs of setting the zero state of the memory elements, from the second to the (n-1) -th group, are combined and connected to the input from the zero-setting state of the n-th 4: memory element of the k-th group, the output of the p-th element of the AND group, where p 1,2, ..., p-2, is connected to (p - "- 1) -th oo input of the k-ro element OR zeroing, the outputs of the multi-input elements of the bits of the bit analysis are connected to the inverse inputs of the multi-input element AND, the output of which is the output of the end of the device search, the output of the first multi-input element of the bits of the analysis of bits is connected to the inv The transverse input of the second control element I, the first inverse input of the pth element AND of the analysis of bits is connected to the output of (p + 1) -th

Description

of the go-through element OR analysis of bits, the second inverse input of the first element AND analysis of bits is connected to the output of the first multi-input element OR analysis of bits, the output of the p-th element AND the analysis of bits is connected to the third input of the (p + 2) -th control element And the second input (p + 1) -th element And analysis of bits.

one

The invention relates to automation and computer technology and can be used in various digital information processing devices, sample recognition devices, devices processing spectra of complex signals.

The aim of the invention is to improve the speed of the device.

The drawing shows a block diagram of the proposed device.

The device contains gp groups of elements And,, 1, 1, ....

1.i:;, 1, ...... C, m; groups

memory elements 2.2 .... 2.2,

2 9 9 TTQ. “,,, ele

cops OR 3% 3, ....., 3 zeroings, p-multiple input elements OR analysis of bits 4.Ag4, control elements AND 5, 5 ... .5 ,, (n-2) elements AND analysis of discharge Dov 6

, INPUT 7 start up device 2

The pulse generator 8 pulses, the multiple-input element AND 9, the result register 10, the (ri-1) elements, and the zeroings 11, 11, 11n-1 (1), the inputs 12, 122 ... 12, and elements 11j are the second settings in the zero state of the jth group of memory elements 2j, 13 is the output of the device search end.

The purpose of the elements of the device is as follows. Memory elements 2 where

one;. 1,2, ...., t, t 1,2, ..., n, tn the number of analyzed binary numbers, n - the number of binary bits in a number, are used for temporary storage of binary numbers. ) -a group, pa elements AND 1 j L element OR 3 are used to generate a zero reset signal for the 1st group of memory elements 2. If, when gating a signal from the output of the element 5 of the first element 1 and 1, in the corresponding group, the bits of the binary number stored in the corresponding memory cell are zero, then all the memory elements storing the number are zeroed out. The elements of OR 4 form

resolution resolutions, for example

Whether at least B ONE of the numbers of the analyzed bit is present in the elements 2 of the memory 1.

Elements And 5, where i 1,2, ..., p and elements And 6p, where p 1,2, ..., (p-2) serve for the sequential analysis of the bits of all numbers and the corresponding gating of those bits, which contain at least one of the numbers 1 in the corresponding category.

Element AND 9 serves to generate a signal for the end of the search operation for the maximum number at the output 13 of the device, and the output signal

And 9 appears only under zeroed conditions of all 2 memory elements, i.e., when there are no permission signals from the outputs of I1Sh 4- elements.

Elements And 11; where j 1,2,

(p-1) are used to generate a zero signal for the corresponding bit of the second group of memory elements 2

. to the end of the cycle of rewriting 1 state in the register 10 of the result.

Result register 10 serves to form the binary n-bit code of the maximum of m binary numbers.

The pulse generator 8 serves to generate synchronization cycles, ensuring the sequential formation of gating pulses in the analysis of number bits, starting with the higher bits. The start of the generator 8 occurs on a signal received at the input 7 of the launch device.

3

The device works as follows.

Before you start working in elements

You 2 V memories bring mc binary numbers, and in the first group of 2 memory elements all the leading bits of m binary numbers are entered, then all subsequent numbers of numbers in the order of decreasing precedence of bits are added to the next groups, and The elements of 2 memories are scored by all the lower-order bits of m binary numbers. The result register 10 is reset.

Into the device, at input 7, a start signal of the operation is received, which starts the generator of 8 pulses. The pulse generator 8 generates a series of gating pulses dp of the elements And 5, element 9, elements 1 b, and the resolution signal for elements 5 and element 9 and 9 is the clock itself, and for elements 11 the absence of a clock pulse on them first entrances.

In case 1, if at least in one of elements 2 of the memory of the 1st group, where 1 1,2 ,, t, 1 is recorded in the highest order, then the signal through the element OR 4 goes to the second input of the element And 5, allowing passage of the strobe pulse from the generator 8 pulses. In this case, the signal enters the result register 10 and writes 1 to it in this bit, and also this signal goes to the second inputs of the And 1 elements of this bit. If in the I.-OM number, 1 1.2, .m, this bit is set to the O state, then the inverting potential, opening AND 1 elements, is removed from the inverse output of the memory element 2, and the signal of the zero setting the state of the first inputs of the memory elements 2, in which the tc-oe number is stored. This number is excluded from the process of finding the maximum of m binary numbers. At the end of the first pulse, the generator of 8 pulses at the first input of the element 11 has a resolution signal, and since the first clock in the high register register 10 has already been recorded 1, the element 11 11 is triggered and at its output 12 a setting signal appears null734084

The current state of all the higher bits of memory elements 2, i.e. analyzed bits of elements 2. memory is zeroed. 5 In case 2, when studied

Since the numbers have zero values in the higher order (), then the output of the OR 4 element to the second input of the AND 5 element receives the Ban 10 signal and the third input of the AND 5 element already allows this signal (it is inverted at the input). At the same time, if at least one of the numbers in the next bit () is 1, then the OR 2 element is triggered, thereby allowing the first strobe from the generator 8 to pass through the second element AND Sj. The element And 5 and the signal from its output 0 trigger. enters the result register 10 and writes 1 to this bit, as well as to the second inputs of the elements AND 1 where 1 1,2, .... t. If the number of this bit is zero, then

5, the inverting potential, which opens, is removed from the inverse output of the MEMORY element 2 of this bit. . the element AND 1 and through the element OR 3 the signal is set to zero

0 state by first inputs of elements. There are 22 memories in which the k-oe number is stored. Thus, already the first strobe pulse is used to rewrite a single value after

of the next bit in the register 10 results in the presence in all of the most senior bits () numbers of zero values. Those elements of the memory of those numbers that did not have

Q of this gated bit value as in the previous case. At the end of the strobe pulse, the memory elements of the prostrated bit of all numbers are reset.

In case 3, when both in the highest and. In the subsequent bits (,) there are only zero values in all studied numbers, then from the output of elements SHSh 4 and 4, the second inputs of the corresponding elements And 5 and 5 are prohibited. These same signals from the outputs of the elements OR 4 and 42, such as zero potential,

J already cause the triggering of the element ШШ 6 due to the inversion of the signals arriving at its inputs. The resolving potential from the output of the element OR 6 allows the triggering on the third input of the element AND 5 and on the second input of the element AND 6. Further, if at least one of the numbers has the next digit () set to 1, then the element OR 4 and the second input of the element AND 5- the resolution signal. The first strobe pulse is overwritten by 1 in the corresponding register register 10 of the result, and all the memory elements of the numbers that had () bit zero value are reset in the same way as in the preceding cases. At the end of the strobe pulse from the output 12j of the element 11z, the signal is zeroed, all the elements are 2 memories (). Similarly, analysis and gating of subsequent bits is performed.

Next, the analysis and gating of the next j-bits w numbers, recording 1 in the corresponding bits of the result register 10, if at least one analyzed j-bit of the investigated 1. numbers was 1. If in the -th number the j-th bit d is zero, then the inverse output of the memory element 2 of this bit enters the resolution sequentially in the appropriate cycle through the AND 5j element, the first element AND 1 OR element 3 to be set to the zero state on the first inputs of the memory elements 2j, in which stored number. At the end of the strobe pulse, the memory elements 2 of the tested j-bit of all m numbers are reset to zero.

Thus, the analysis of the significant (non-zero) number bits and the transfer of the gating cycle to the first significant bit is performed, thereby reducing the time required for generating the result in the register 10. In addition, in each cycle all numbers that have gated in the gaps are reduced from the analysis dah zero, and all analyzed significant bits are zeroed. Moreover, in each cycle of pulses from the pulse generator 8. a survey is performed ... of the states of all the bits of all the numbers on O. If in the polling element I 9, a pulse will arrive at its gate at the moment when all the numbers have left the analysis, and the maximum Since the number has a zero value in the remaining bits, then a signal about the end of the operation is generated at the output of the AND 9 element. This allows you to prematurely determine the maximum number, while the number N of clock pulses is less than the number n bits of the numbers being examined. As a result of searching for the signal from the output 13 of the device in register 10, the generated binary code of the maximum tn binary numbers can be written to the external device.

Introducing the composition-adaptive synchronization information, when polling the number bits, taking into account the analysis of the significant (single value) number bits, zeroing the corresponding memory elements of the analyzed bits of all numbers, analyzing the zero states of the memory elements allows increasing the real speed of the device, reducing time to search for an extremal number from m binary numbers.

Claims (1)

A DEVICE FOR DETERMINING THE MAXIMUM OF m BINARY NUMBERS ', containing tn groups of elements AND of n-1 elements AND in each group, where η is the number of bits of the compared numbers, tn are groups of memory elements by η memory elements in each group, η are multi-input elements OR analysis bits, m elements OR zeroing, control elements AND, the register of the result, and the direct output of each i-ro memory element to the ~ th group, where <= 1,2, ..., n, k = 1,2, .. .., tn is connected to the k-th input of the i-ro element OR analysis of the discharge, the output of which is connected to the first input .i-ro of the control e element And, the output of which is connected to the unit in the i-ro state of the discharge register of the result register, the output j-ro of the control element And, where j = 1,2, ..., p-1 is connected to the first inputs of the ix elements AND of all groups , the second input of the j-ro .. element of the kth group is connected to the inverse output of the j-ro memory element of the kth group, the output of the (n-1) th element of the kth group is connected to the first input of the kth element OR zeroing, the output of which is connected to the zero input of the ηth memory element of the kth group, characterized in that, in order to improve performance, η-1 elements And zeroing, η-2 elements And discharge analysis, a multi-input element And and a pulse generator, the start input of which is connected to the start input of the device, and the output is connected to the second inputs of all control elements And, the control input of the multi-input element And and inverse inputs of all elements And zeroing, direct input <q j-ro of the element And zeroing is connected, to the output j-ro of the discharge register of the result, and the output is connected to the first inputs of setting to zero state jx memory elements of all groups, the second inputs settings in the zero state of memory elements from the second to the (n-1) th k-th group are combined and connected to the input of the installation in the zero state of the p-th memory element of the k-th group, the output of the r-th element And to ~ group, where p = 1,2, ..., n-2, is connected to the (p + 1) -th input of the k-th element OR zeroing, the outputs of the multi-input elements OR of the discharge analysis are connected to the inverse inputs of the multi-input element And, the output of which is the output of the end of the device search, the output of the first multi-input element OR discharge analysis is connected to the inverse input of the second AND control element, the first inverse input of the r-th element AND of bit analysis is connected to the output of the (p + 1) th multiSU. „1173408 of the input element OR of bit analysis, the second inverse input of the first element AND of bit analysis is connected to the output of the first multi-input element OR the analysis of discharges, the output of the rth element AND of the analysis of discharges is connected to the third input of the (p + 2) th control element And and the second input of the (p + 1) th element of And analysis of discharges.