SU1172056A1 - Device for checking failures of pseudorandom test signal - Google Patents

Abstract

1. A DEVICE FOR MONITORING FAILURES of a Pseudo-Random Test Signal, which contains an integration unit, a pseudo-random signal generator, a clock generator, an input switch, two serially connected main modulator two and a D-flip-flop, sequentially connected second modulators of the two moduli and two -trigger, serially connected first delay unit and additional modulo two, sequentially connected second delay unit and additional modulo two , the first signal inputs of the first and second main modulators are two connected to the corresponding outputs of the pseudo-random signal generator, the first output of the clock generator is connected to the first control input of the input switch and the clock inputs of the pseudo-random signal generator, the first and second U triggers, first and second blocks. delays, the second output of the generator, the clock frequency is connected to the second; the control input of the input switch, the first output of which is connected to the second signal input of the second main modulo two and to the signal input of the second delay unit, the second output of the input switch connected to the second signal input of the first main modulo two and the signal input of the first block delays, the outputs of the first and second C-flip-flops are connected respectively to the second inputs of the first and second (There are two additional modulators, the outputs of which are connected to pseudo-random signal generator, the output of the first main modulo-two adder is connected to the input of the integrator, the output of which is connected to the reset input of the first and the HS of the second P-flip-flops, which, in order to increase the reliability while about automating the monitoring of flow failure parameters, N counters have been entered into it, where N is the NUMBER of signal processing channels, the time stamp generator connected in series and the time stamp counter, the control unit and the serially connected th computing unit and the display unit, the signal inputs of the counters connected to the outputs of the respective first and second D -triggerov, shifting each subsequent counter inputs connected to shearing

Description

the outputs of each previous counter, shifting the output of the first counter is connected to the shifting input of the time stamp counter, shifting the output of which is connected to the shifting input of the last counter, the address output, the request output and the input of the sync pulse of the computing unit are connected respectively to the address input, the query input and the sync pulse output the control, the inputs of the prohibition of the account, the reset and the control of the shift of the counters and the counter of time stamps are connected respectively to the outputs of the prohibition of the account, the reset and control unit of the control unit, the prohibition input of which is connected to the output of the integration unit, the synchronizing inputs of the meters are connected to the first

72056.

generator output clock frequency.

, 2. Device pop. 1, characterized in that the control unit is made in the form of an OR element, serially connected decoder, AND element and pulse generator, the first input of the OR element is connected to the first output of the decoder, the second output of which, as well as the outputs of the OR element The pulse generator and the element And are respectively the output of the reset, the output of the prohibition of the account, the output of the shift control and the output of the sync pulse of the control unit, the address input, the input of the request and the input of the prohibition of which but the decoder input, the second input of the AND and the second input of the OR element.

one

The invention relates to a measurement technique in digital communication lines and can be used to detect failures of a test pseudo-random signal at the input of the communication line, as well as at the output of the communication line.

A feature of the proposed device is that it is intended for communication lines with a speed of over 140 Mbit / s, in which technical means of less high-speed communication lines cannot be used due to insufficient speed.

The purpose of the invention is to increase the reliability while simultaneously automating the monitoring of the parameters of the flow of faults.

Fig. 1 shows a structural electrical circuit of the proposed device, Fig. 2 shows a control unit, an option.

The device for monitoring failures of a pseudo-random test signal contains a pseudo-random signal generator 1, consisting of thirteen D-triggers 2-14 and two modulo-two adders 15 and 16, a clock generator of 1-7, the input

the switch 18, the first and second adders modulo two are 19 and 20, the first and second delay blocks 21 and 22, the first and second modulators are two 23 and 24, the first and second D triggers 25 and 26 are the integration block 2.1, the short-circuit short-circuit filter 28 and the threshold element 29, N counters 30 -30j, the display unit 31, the time stamp counter 32, the time stamp generator 33, the control block 34, the computing unit 35 ..

The control unit 34 contains (Fig. 2, a decoder 36, an element OR 37, a generator 38 of bursts of pulses and an element AND 39.

The device works as follows.

The analyzed signal in the form of an M-sequence is fed to the input of the input switch 18, which in this case performs the conversion from the serial code at the input to the two-bit binary parallel code at its outputs. Moreover, at each output of the input switch 18, the duration of the code pulse is equal to two clock intervals, the signal arriving at the input of the second modulo two 20 adder corresponds to the Spi-i signal in the first half of the previous push-pull interval, and the signal arriving at the input of the first adder according to module two 19 - to signal 5 in the second half of the previous two-cycle conversion from the serial code at the input to the parallel code at the output of the input switch 18. The beginning of the two-stroke interval is set by voltage m half-cycle frequency from the generator output 17 clock frequency. (Generator 1 is part of the regeneration equipment of the line under investigation, or it is a special clock frequency selector in the proposed device, similar to the clock frequency selectors of regenerators). Denote 5 and 5 | ,. respectively, as codes of the signals at the outputs of the first and second E-triggers 25 and 26, similarly to the Sp codes, and 5. in the first and second halves of the two-stroke interval specified by the voltage of the semi-clock frequency from the output of the 17 clock frequency generator. Express codes Z. and 5 through 5 ,, and 5 „and the delay operator X. Since the delay in each of the B-triggers 2-14 of the generator 1 and the first and second delay blocks 21 and 22 is equal to two clock intervals, the delay operator in them is expressed in the form of X. The proposed device can operate in two modes. Synchronization mode, when the first and second D-triggers 25 and -26 are reset to the zero state by a pulse generated at the output of the threshold element 29 of the integration block 27 Fault measurement mode, when logical voltage levels at the outputs of the first and second D-triggers 25 and 26 vary in accordance with the signals at the inputs of the first and second modulators two 19 and 20, since the logic level of the output voltage of the threshold element 29 is zero. The output for codes S ,, and 5p is obtained at the outputs of the second and first adders modulo two 20 and 19 in the first and second halves of the two-stroke interval in the synchronization mode, at which from the output of the first adder modulo two 19 on the Ix of the integration block 27 continuous stream of error pulses. At the output of the integration unit 27, a logical unit level signal is generated, which resets the first and second D triggers 25 and 26 to the zero state. The indicated error pulse stream is generated because the signal recorded in the D triggers 2-14 of the generator 1 at the moment the device is turned on, does not correspond in structure to the pseudo-random sequence received at the input of the input switch 18. In this case, the signal code 5 is expressed modulo two codes at one input of the second modulo two 20 and output codes e B-flip-flop 9 of generator 1, which can be expressed in the following form, O) where the expression in brackets corresponds to the code at the output of the modulo-two 15 generator 1, which is the result of summing the 5n code on its first and second inputs. Then the ratio 5:,: 9 „., 0„ x% 5 „x - is valid. (Y, Similarly, it can be calculated that the code at the output of the first modulo two 19 5 adder is expressed as 5: 5 "P5" -, X .5 "., X) .5"., X. P-1 Ced 5 is the result of delaying a pseudo-random signal by one clock cycle. Therefore, using the delay operator X, we can write the relation, substituting which in (2) and (3), we obtain the expressions., U). s; .s, t.), U) - / 1 / f in which the polynomial 1 + X + X corresponds to the generator polynomial of the 1 pseudo-random signal in the form of M-sequence. If a 5.1 5p pseudo-random signal is generated by generator 1

with the feedback structure described by the generating polynomial l + X + X and does not contain failures, then 5π and 5 ,, are equal to zero. In this case, at the reset inputs of the first and second

The D-triggers 25 and 26 will set the voltage to a logical zero, since the zero voltage is applied to the input of the integration unit 27, and therefore to the input of the low-pass filter 28. As a result, the first and second D triggers 25 and 26 will function as delay blocks. The device enters the fault measurement mode.

If, in this case, deviations appear in the pseudo-random signal (faults

B compared to the reference M-sequence, that is, if

n-1 2m (().

 ,

(ft)

where 5m (n-1) and 5, y, p | - the corresponding code value for the M-sequence in the first and second halves of the two-stroke interval,

 j and n are similar for M-sequence failures, then error signals 5 |, 1, appear at the inputs of the first and second D flip-flops 26 and 25, which change the logic levels of the incoming input signal 5 g, .-, 5 When In this respect, the reference pseudo-random sequence recorded previously in generator 1 does not change. Due to this, at the outputs of the first and second D-triggers 26 and 25, error signals (malfunctions) are distinguished 5 | corresponding to the signals of failures -n-1 I p input test pseudo-random signal. The structure of the bursts of malfunction in this case is recorded without distortion, and I signals appear at the outputs of the first and second D-flip-flops 25 and 26

3;., N-,. (9) the first of these corresponds in time to eEy, the arrival of the first half of the two-stroke interval, and the second half of the second half of the two-stroke voltage interval. half-cycle frequency

We now show how in the proposed device weekend

signals 5 (,., 5, expressed through the input signals Sn-i Sn of the proposed device operating in the fault measurement mode, the following system of equations can be written

5n4Sn S, o) i Xto)

i,

Sn.1 () X

(-111

S3 (5,) X (uX) (n)

: 5, o45n -,) X (13)

where S (j, Sg - signals on the waves)

B-flip-flops 10 and 9 of generator 1,

From the system of equations (10) - (13), the following equations for S, can be obtained. and Sn

Sn - S. (,.). 5U (X «.); (AND

5; -., (). S (x-.x-), 05

whence it follows that in view of (4)

.. W

5.5,)) - (17)

Multiplication by the generating polynomial .1 + Xi of equations (16) and (17) means the allocation of errors p., F, / cm, (7) and (8) 7 from the received M-sequence. Therefore, equations (16) and (17) for ti-i, tn failures can-be after the corresponding transformations written in the following form

HRH- C-n-iX. (18)

where fcI, ..,, ЕП - signals of errors (faults) at the outputs of the first and second D flip-flops 25 and 26, Equation (18) show that error signals at the outputs of the first and second D-triggers 25 and 26 are delayed by two clock intervals in relation to the error signal (failure) in the input sequence, however, the structure of the output error pack is fully consistent with the structure of the input error packet. Due to the fact that the modulators present in the device are nowhere directly connected to each other, since they are separated by D triggers, the sum of the delays in the modulo adder two Сд and in the D trigger f is necessary for the device to work. double clock interval 2T, i.e. Cj + TD 2G. (19) If V is NA, then the maximum value of the clock frequency is 250 MHz. As the experiments show, with the existing paternal element base (integrated circuits of the 100, 500 and 570 TM1 series), counters 30 can be built with a maximum counting rate of no more than 220 MHz. However, for ultra-high-speed digital communications, it is necessary to ensure the operation of the device at the following discrete clock frequency values: 140, 280, 560 and 1200 MHz. Since the development of an apparatus for a t-current frequency of 140 MHz can be accomplished by already known means, the next task is to achieve speeds of 280 and 560 MHz. Here, the limiting factors are the insufficient maximum speed of information shift in the pseudo-generator pseudo-random signal (160 MHz) and the insufficient speed of the counter 30 (220 MHz). In the proposed device, designed to register pulse faults following at a frequency of up to 280 MHz or more, there are at least two pulse counting channels. The counting inputs of the counters receive pulses of failures in the parallel code from the outputs of the first and second D-flip-flops 25 and 26. The beginning of the counting interval is set automatically by the processing program of the computational unit 35, which by address bus sends to the control unit 34 a byte combination arriving at the decoder 36, from the output of which the signals cause the reset of the counters and the counter 32 timestamps. After the reset pulse is removed, the counters go into counting mode. If, at the same time, the zero of the signal level to the OR 37 terminal (Fig. 2) from the threshold element 29 arrives at the inlet of the control unit 34, then from the control unit 34 to the inputs of the prohibition of the counting of the counters 30 and the counter 32 there is no voltage level prohibiting the counting pulses. If the signal level at the input of the prohibition of block 34 corresponds to a logical one, then in block 34 a signal is generated that prohibits the counting of pulses in the counters 30 and the counter 32. The counting prohibition from the threshold element 29 occurs when the device is turned on when processes occur in the pseudo-random generator state of synchronization, as well as when i is synchronized during normal operation from the generator 17. In this case, a packet of long duration failures occurs, which does not reflect the actual state and the communication channel. The presence of the communication unit 34 with the threshold element 29 prevents the registration of parasitic packets of failures, which also improves the accuracy of the registration of failures by the proposed device. After a predetermined time interval, the computing unit 35 generates a combination of Shift signals on the address line, under the action of which the control unit 34 prohibits the counting of pulses in the counters 30, -30 and the counter 32, and at the instant of the appearance of the back positive edge of the information request from the computing unit 35 The pulses of information shift control from the output of the generator 38 of the block 34 are output to the inputs of the information shift shift in the counters. Under the action of these pulses in the counter and counter 32, a cyclic shift of information occurs. After the completion of the next cycle of information shift in the counters and the counter 32, the computing unit 35 stores information on the shift bus of the counters 30-30. After the shift of the information in the counters 30 and the counter 32, the computing unit 35 removes the information corresponding to the shift of the address bus. When, this information in the counters 30 - 30 i t and

and the counter 32, after a complete shift cycle, returns to the corresponding counting stages, and the proposed device again goes into

pulse counting.

Thus, in the memory of the computing unit 35 there is information about the number of pulses recorded by the counters 30-30 and the time stamps recorded in the counter 32 from the generator 33. The sum of the readings of the counters 30 gives the total number of faults during the measured interval. The readings of the counter 32 correspond to the number of clock intervals per measurement interval. The information obtained allows the processing site to continuously receive information on the frequency of failures in the canape, on the law of distribution of failures in the communication channel, on the presence of batches of failures, on the correlation of failures. If the impulses of failures follow through a period, then at the input of the counters 30–30, one long pulse is formed, which leads to errors in the registration of numbers. wa failures. In practice, such a situation is extremely rare, since in digital communication lines the reliability of information transfer must be high (the probability of errors is not worse than 10), and failure occurs once (take one clock cycle). l elimination of registration errors in case the faults take several clock intervals, the counters 3Q, 30f must be synchronous ,. and Synchronization comes from the clock input of the generator 1 pseudo-random signal. In this case, the counters 30 count the number of clock intervals that the incoming and outgoing signals of the first and second 3) triggers 25 and 26 are applied to. An increase in the signal clock frequency in communication lines to 280 MHz requires the use of a consideration. of the proposed device, and the subsequent increase in the frequency up to 560 MHz to the four-channel scheme of the device, at which two additional counters must be added and, accordingly, the connection change in the generator 1 of the pseudo-random signal.

The control unit 34 comprises a decoder 36, a pulse burst generator 38, an AND 39 element and an OR 37 element. The signal inputs of the decoder 36 are connected to the address inputs of the control unit 34. The decoder has the Shift and Reset outputs, the pulses of which appear in the corresponding states of the address line of the computing unit 35. The Reset Output is connected to the Control Reset output of the block 34, and the output

Shift - to the input of the element OR 37, another input of which is connected to the inhibit input of the block 34. The output of the 1SH element 37 is connected to the output of the invoice for block 34. The output of the Shift is also connected to the input of the AND 39 element, the other input of which is connected to the input of the request of block 34 The output of the element And 39 is connected to the output of the clock pulse unit 34. In addition, the output

element AND 39 is connected to the input

generator 38 packs of pulses. The generator 38 should produce at each output one pulse at the positive front of each of

request pulses of block 34. Therefore, the generator 38 can be implemented in the entire shift register or on the basis of a counter, a decoder of the crystal oscillator and the AND circuit in feedback using known schemes of this kind.

je

g8

J9

FIG. 2

Claims (2)

1. DEVICE FOR CONTROL OF FAILURES OF AN ESSENTIAL TEST SIGNAL, comprising an integration unit, a pseudo-random signal generator, a clock generator, an input switch, the first main adder modulo two in series and the D-flip-flop, the second main adder modulo two and sequentially connected D-flip-flop connected in series to the first delay unit and an additional adder; modulo two, in series connected second delay unit and. ; additional adder modulo • two, the first signal inputs of the first and second main adders modulo two are connected to the corresponding; outputs of the pseudo-random signal generator, the first output of the clock generator is connected to the first control input of the input switch and the synchronizing inputs of the pseudo-random signal generator, the first and second B 1 .. flip-flops, the first and second delay units, the second output of the clock generator is connected to the second control input of the input switch, the first output of which is connected to the second signal input of the second main adder modulo two and to the signal input of the second delay unit, the second output of the input switch is connected to the second the signal input of the first * main adder is modulo two and to the signal input of the first delay block, the outputs of the first and second D-flip-flops are connected respectively to the second inputs the first and second additional adders modulo two, the outputs of which are connected to the corresponding inputs of the pseudo-random signal generator, the output of the first main adder modulo two is connected to the input of the integration unit, the output of which is connected to the reset input of the first and second D-flip-flops, In other words, in order to increase reliability while simultaneously automating the control of failure flow parameters, N counters are introduced into it, where N is the "number of signal processing channels connected in series by the generator etok time counter and time stamp, and the control unit are connected sequentially computing unit and display unit, the signal inputs of the counters are connected to the outputs of the respective first and second D -triggerov, shifting each subsequent counter inputs are connected to the shearing * 950 ШГ П5 with the outputs of each previous counter, the bias output of the first counter-4 ka is connected to the bias input of the time stamp counter, whose bias output is connected to the bias input of the last counter, the address output, the request output and the input input of the clock pulse of the computing unit are connected respectively to the address input, input the request and the sync pulse output of the control unit, the inputs of the prohibition of counting, reset, and control of the shift of the counters and the counter of timestamps are connected respectively to the outputs of the prohibition of counting, reset and shift control of the control unit, the inhibit input of which is connected to the output of the integration unit, the clock inputs of the counters are connected to the first output of the clock frequency generator. 2. The device according to claim 1, characterized in that the control unit is made in the form of an OR element, decryptor connected in series, AND element and pulse train generator, the first input of the OR element connected to the first output of the decoder, the second output of which, as well as the outputs of the OR element , a generator of bursts of pulses and an AND element, respectively, are a reset output, a counter inhibit output, a shift control output and a control unit clock output, an address input, a request input and a ban input of which are respectively turn the decoder, the second input of the AND and the second input of the OR.