SU1169009A1 - Device for displaying information - Google Patents

Abstract

1. A DEVICE FOR DISPLAYING INFORMATION containing a data distributor, whose input is the information input of the device, and the first output is connected to the first input of the register, the second input of which is connected to the first output of the control unit, the second and third outputs of the control unit are connected to the control input of the generator characters and the first control input of the video signal generator, respectively, the output of the video signal generator is the output of the device, the second control input is connected to the output of the adder p Module two, the first and second information inputs are connected to the outputs of the symbol generator and register, respectively, characterized in that, in order to increase the reliability of the device by detecting faulty situations, it contains five memory blocks, the information input of the first of which is connected to the first information the input of the second memory block and the data distributor input, the control input of the first memory block is connected to the fourth input of the control unit, and the output is connected to the information input of the character generator, the third info The input of the video signal maker and the input of the modulo two. the first decryptor, the input of which is connected to the input of the data distributor, the priority block, the inputs of which are connected to the output of the first decoder, the second output of the data distributor and the output modulo two, and the outputs to the control inputs of the second, third and fourth memory blocks, block rewrites, the control inputs of which are connected to the output of the first decoder and one of the outputs of the priority block, and the first information output is connected to the information inputs of the third and fourth memory blocks and the second information the second input memory block, a group of OR elements whose inputs are connected to the outputs of the second, third, and fourth memory blocks, and the outputs to the first information inputs of the fifth memory block and (L rewriter block and digital-analog converter, output which is the signal output of the device, and the input is connected to the second information input of the rewriting unit and the output of the fifth memory block, the second information input of which is connected to the second information output of the rewriting unit. 05 2. A device according to claim 1, characterized in that the control unit comprises a series-connected pulse generator and two counters, the outputs of which are respectively the first, second, third and fourth outputs of the block. 3. The device according to claim 1, characterized in that the rewriting unit comprises a second decoder, the input of which is the first information input of the block, and the output is connected to the first input of the first OR element, the output of which is connected to the first input of the third counter, the output of the third counter is The first information output of the block and the second input are connected to the output of the second OR element, the first input of which is connected to the first input of the fourth counter and the output

Description

The third decoder, the input of the third decoder and the output of the fourth counter are respectively the second information input and the second information output of the block, and the second input of the fourth counter is connected to the output of the generator, and the second inputs of the OR elements are the control inputs of the block.

one

The invention relates to automation and computer technology and can be used to display information about the progress of a fast-flowing process distributed over a large area.

The aim of the invention is to increase the reliability of the device by detecting faulty situations.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a functional block diagram of the control unit; in fig. 3 - functional block rewriting scheme.

The device contains a control unit 1, a register 2, a generator of 3 symbols, a video signal shaper 4, a data distributor 5, a first memory block 6, a modulo-7 adder two, a priority block 8, an overwriting block 9, a first decoder 10, a second 11, a third 12 and the fourth 13 memory blocks, the group of elements OR 14, the fifth block of memory 15, the digital-to-analog converter 16, the pulse generator 17, the first 18 and second 19 counters, the second decoder 20, the first 21 and second 22 elements OR, the third counter 23, generator 24, fourth counter 25 and third decoder 26.

The device works as follows.

Information about the technological process from an external device (computer) comes in the form of information words to the first memory block 6, data distributor 5, the second memory block 11 and the first decoder 10. After recording the information in the first memory block 6 to the 3 character generator and the adder 7 modulo two of the memory block 6, by a signal from the control block 1, the character codes and the color codes are received. From the output of the character generator 3, the video signals of the characters are transmitted via the first information input to the video driver 4. Modulo 2 modulo two checks the information words for evenness, and when an error is detected, the signal from the adder output is fed to the second control input of the imaging unit 4 of the video signal.

The information supplied to the data distributor 5 from an external device is accompanied by address words. Absolute addresses are recorded by a data distribution counter. Next, the information parcel is analyzed by the control circuit of the data distributor 5, and, if there is an error at the recorded address, the control circuit issues a signal to allow the address to be written from the counter to the register

2. From the output of the last error information is fed to the second information input of the video signal generator 4 and at the same time the error signal from the distributor 5 is fed to the input of the priority block 8.

The signal from control unit 1 sends signals from the first memory unit 6 to the imaging unit 4 of video signals in the form of character color codes, character video signals from the 3-character generator, error control signals from modulator 7 and two and information from register 2 (errors in the channel zi). Shaper 4 video signals converts the video signals of the characters and the color code of the character into red, green and blue video color signals, which are output to the device.

The control unit 1 generates the synchronization and control signals of the video signal generator 4 and the register 2 and the address signals for reading information from the first memory block 6 and the 3 character generator. Simultaneously with displaying the information, the second memory block 11 from the external device promptly records information in the form of phoneme codes, phrases, for example, an "alarm condition

5 of the first unit. At the same time, in addition to the code parcels, the end-of-phrase code is transmitted at the end. After each information of the parcel, control pulses arrive at the rewriting unit 9. At the same time, from the first decoder 10 (the end of the phrase), a resolving impulse comes to the priority block 8.

Thus, a technological process is displayed on the screen of a CRT, and errors and malfunctions in the technological process are distinguished by the blinking of the corresponding elements. However, from the visual information on the screen it is impossible to determine where in the system the error occurred, i.e. in a process, communication channel, or display device. In order to manage high-speed technological processes dispersed over a large area, it is very important to receive information about emergency situations in real time. Therefore, the task is to recognize emergency situations with operator notification by voice prompt in real time, taking into account priority. For such processes, the highest priority is the process. The information playback mode on the CRT screen is combined with the information analysis mode in the error control block and the logic block. Information about possible errors is pre-programmed in the third 12 and fourth 13 memory blocks. In the fourth memory block 13, phrase phrase phone codes are stored, for example, "Error in the communication channel, phrase end code, in the third memory block 12 - phrase phone codes" Error in display device, phrase end code. The priority of the second 11, third 12 and fourth 13 memory blocks is determined by the priority block 8, whose operation is explained by the truth table. Inputs Outputs 6 13 In this unit, the highest priority is represented by the second memory block 11. Depending on the importance of the information, the priority can be changed by switching the outputs of the priority block 8. Block 9 rewriting works as follows. With the arrival of the enabling signal from the priority block 8, the generator 24 is started up at the input and the fourth counter 25 begins to generate addresses for the fifth memory block 15. When the addresses arrive at the fifth memory block 15, a discrete code and a phoneme code appear at its output. In this case, the discrete code is converted by the digital-to-analog converter 16 and is fed to the output of the device for conversion to a speech signal. The code of the end of the phoneme is converted by the third decoder 26 (the end of the phoneme) into a pulse to reset the fourth counter 25 volts. At the same time, the pulse of the third decoder 26 through the second element OR 22 is fed to the second input of the third counter 23. After reading the phrase, the code of the phrase end enters the input of the second decoder 20 (end of phrase) and the output pulse from the decoder through the first element OR 21, the third counter 23 is reset to. When synthesizing the information recorded in the second memory block 11, the third counter 23 is reset to "About the signal from the first decoder 10 (end of phrase) via the other input of the first element OR 21. Thus, the phrase is synthesized. Addresses for reading information from the second memory block 11 and synthesis of phrases come from the rewrite block 9. If there are errors or failures at one or all levels, errors are marked by the blinking of the corresponding elements. The priority block determines the most important information and issues an enabling signal to synthesize a phrase corresponding to this information for the voice prompt. Simultaneously with the phrase playback, the indicator light is on, symbolizing the operator for the occurrence of an error or failure.

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Claims (3)

1. DEVICE FOR DISPLAYING INFORMATION, containing a data distributor, the input of which is the information input of the device, and the first output is connected to the first input of the register, the second input of which is connected to the first output of the control unit, the second and third outputs of the control unit are connected to the control input of the symbol generator and the first control input of the video shaper, respectively, the output of the video shaper is the output of the device, the second control input is connected to the output of the adder mode two, the first and second information inputs are connected to the outputs of the symbol generator and register, respectively, characterized in that, in order to increase the reliability of the device by identifying malfunctioning situations, it contains five memory blocks, the information input of the first of which is connected to the first information input of the second block memory and the input of the data distributor, the control input of the first memory unit is connected to the fourth input of the control unit, and the output to the information input of the symbol generator, the third information the input of the video signal shaper and the input of the adder are modulo two, the first decoder, the input of which is connected to the input of the data distributor, a priority block whose inputs are connected to the output of the first decoder, the second output of the data distributor and the output of the adder modulo two, and the outputs to the control inputs of the second , of the third and fourth memory blocks, a rewriting unit, the control inputs of which are connected to the output of the first decoder and one of the outputs of the priority block, and the first information output is connected to the information the inputs of the third and fourth memory blocks and the second information input of the second memory block, a group of OR elements whose inputs are connected to the outputs of the second, third and fourth memory blocks, and the outputs are with the first information inputs of the fifth memory block and the rewriting block, and digital-to-analog converter, the output of which is the signal output of the device, and the input is connected to the second information input of the rewriting unit and the output of the fifth memory unit, the second information input of which is connected to the second information nnym yield rewriting unit. 2. The device according to π. 1, characterized in that the control unit contains a series-connected pulse generator and two counters, the outputs of which are respectively the first, second, third and fourth outputs of the block. 3. The device according to π. 1, characterized in that the overwrite unit contains a second decoder, the input of which is the first information input of the unit, and the output is connected to the first input of the first OR element, the output of which is connected to the first input of the third counter, the output of the third counter is the first information output of the unit, and the second input is connected to the output of the second OR element, the first input of which is connected to the first input of the fourth counter and the output SU 1169009 of the third decoder, the input of the third decoder and the output of the fourth counters are respectively the second information input and the second information output of the block, and the second input of the fourth counter is connected to the output of the generator, and the second inputs of the OR elements are the control inputs of the block.