SU1597895A1 - Device for displaying information on color tv monitor - Google Patents

Abstract

The invention relates to automation and computing and can be used to display graphical information from a computer. The purpose of the invention is to increase the speed of the device. The device contains write registers 1, read 3 and operating mode 4, memory block 2, digital-to-analog converter 5, address counter 7, television display 6, first 8 and second 9 registers of the selection code, first 10 and second 11 comparison blocks, first 12, the second 13 and third 14 switches, the AND 15 element group, the first 16 and the second 17 OR elements, the AND 18 element, the buffer register 19 with corresponding links. In the mode of image formation through register 1 of entry in block 2 of memory, codes of chromaticity of dots are entered by addresses formed by the counter of 7 addresses. When displayed, information from memory block 2 through the read register 3 and the group of elements AND 15 enters the digital-to-analog converter 5, where color video signals are formed. To control the set of displayed colors, the mode register of 4 modes is loaded with a control code that, controlling the operation of the switches 12-14, allows both to display a fixed set of selected colors on the screen and to set different ranges of colors allowed for display.

Description

The invention relates to the field of automation and computer technology and can be used to display graphic information from a computer.

The purpose of the invention is to increase the speed of the device.

The drawing shows a functional block diagram of the device.

The device contains a register of 1 record block. memory, register 3 readings, register 4 modes of operation, digital-analogue converter (DAC) 5 television indicator 6, counter 7 addresses, first 8 and second 9 registers of the selection code, first 10 and second 11 comparison blocks, first 12 , the second 13 and the third k switches, a group of elements And 15, the first 1b and the second

ten

the devices through register 1 of the record g are transferred to memory block 2 and stored in the corresponding memory cells,

In the read mode, the required address from the device input is fed to the input of the counter 7 addresses, the high-order bits of the address are transmitted to the input address of the memory block 2, and the low-order ones to the input address of the read register 3.

When displaying graphical information from memory block 2, address counter 7 goes through the addresses and generates standard sync signals for color indication of track 6. From the outputs, address counter 7, high-order address bits go to memory block 2, and low-order ones to read register 3 .On block 17, the elements OR, the element AND 18, the buffer is 20 memories in each clock cycle

Ny case 19.

The device works as follows.

The color code of the dots displayed on the screen of the color TV indicator 6 is recorded in the corresponding cells of the memory block 2. The memory unit 2 is designed to store the information of the entire television frame and to ensure the regeneration of the image on the screen of the color indicator 6. The information is read from the memory unit 2 without destroying it. The operations Write, Zero, Read and Display are relative to memory block 2. In order to match the display speed with the period of access to memory block 2, addressing in it is performed by a line element, i.e. an N-P word containing chrominance information from a group of N consecutive image line points. The point in the limits of the line element is addressed in register 1 of the record (in write mode) or in register 3 of the read (in the modes of display, or of reading at the output of the device).

The signals from register 4 output to memory block 2 determine the operating modes of the device.

In the recording mode, the high-order bits of the addresses of the memory block 2 in which information is to be written, from the device input through the counter 7, the addresses are received by a parallel code to the address input of the memory block 2, and the low-end to the input address of the register 1 record. Input color data

s

the devices through register 1 of the record g are transferred to memory block 2 and stored in the corresponding memory cells,

In the read mode, the required address from the device input is fed to the input of the counter 7 addresses, the high-order bits of the address are transmitted to the input address of the memory block 2, and the low-order ones to the input address of the read register 3.

When displaying graphical information from memory block 2, the address counter 7 enumerates the addresses and generates standard sync signals for the color indication of tutor 6. From the outputs, the counter 7 addresses the highest bits ad.

 rez arrive at block 2 of memory, and the younger ones go to register 3 readings. From block 5

WITH

0

five

(

;

the current line element is read. In the period until the next reading of memory block 2 from reading register 3, a sequence of point-by-point information is produced. The DAC 5 generates R-, G-, B-video signals that control the color of the dots of the TV-indicator screen 6. The part of the counter 7 of the address that determines the element number of the line is direct, and the other part that determines the line number, may be direct or reverse counting. The option of maintaining the return counting of the address of the station is preferable, since it provides a simple combination of the following two features of the device: the television frame starts to unfold from the upper left corner of the screen, the construction of the displayed information (for example, graphs) starts from the lower left corner of the screen,

In the initial state of the device i or in the submode of full information display, the logical input 1 arrives at the first input of the first element OR 1b. At the same time, the input data of the chromaticity can be received at the inputs of the DAC 5 and displayed on the screen of a color TV indicator 6 the palette used in the device).

To set the sub-mode of the color-selective display (or the color-selective output of information to the output of the device), the first input of the first element OR-1b is given a selective display signal of the zero level from the register k.

The chromaticity codes from the 3-reading register go to the second inputs of elements of group 15 and 15, as well as to the second inputs of the first 10 and second 11 comparison blocks. Passing the current chromaticity code to the outputs of the AND elements of group 15 is allowed when the signal from the output of the first switch 12 arrives at the second input of the first element OR 1b and then to the first inputs of the AND 15 elements of the group.

The first 8 and second 9 registers of the selection code are designed to record two codes defining the allowed chromaticities. These codes are compared with the current; they are the color code read from memory block 2 in the first 10 and second 11 blocks of comparison, respectively. Three outputs (,,) of each block 10 and 11 of comparison i are connected to the inputs of the third I t and the second 13 switches, respectively. The signals from the output of the second 13 and third of the 14 switches through ele5978Y56

The cops AND 18 and the second element OR 17 arrive at the inputs of the first switch 12.

The intervals of chromaticity values (K) allowed for display are determined by two codes (K1 and K2) j defined in the first 8 and second 9 registries of code selection, as well as

The first 12, second 13 and third 14 switches, controlled by signals from the outputs of the register of the k mode. Let the given codes follow the relation K1: K2. When establishing

, 5 connections of the outputs of the switches 12-1 with their second inputs, the output signal of the switch 12 permits the display of image details with specified chromaticities: K K1 or K K2. The possible 20 sets of states for the first, second, and third switches I-1b, as well as the corresponding intervals of allowed colors for selective display, are given in

2f table.

Thus, the invention provides an increase in the speed of the device when displaying a fragment of an image of specified colors by allowing the ranges to be allowed for displaying colors and dynamically changing them.

Claims (1)

1. A device for displaying information on a color television display screen, containing a recording register, whose information input is the first information input of the device, and the output is connected to the memory input of the memory unit, whose address input is connected to the first output of the address counter, input-output which is accordingly the second information input and the first information output of the device, the output of the memory block is connected to the information input of the reading register, whose address input is connected to the second output of the address counter, the third output of which is connected to the third output of the address estimator, the fourth output of which is connected to the address input of the memory block, the output of the reading register is connected to the first inputs of elements AND of the second group, the outputs of which are connected to the first information inputs of the strobe formation units, the outputs of which are connected to the inputs of the group of the AND element LI, the output of which is connected to the inputs of the first group of the elements and the first group, the outputs of which | connected to the information inputs of the digital-to-analog converter and the buffer register, the output of which is the first information output  159 device home, the second information output and the first information input of which is the information input / output of the address counter, the output of the block of delay elements is connected to the inputs of the second group of elements AND of the first group, the information inputs of the recording registers and masks are respectively the second and third information inputs of the device , the output of the mask register is connected to the second inputs of elements AND of the second group, characterized in that, with the device speed-up circuit, it contains a register of operating modes, The output of which is connected to the control input of the memory unit, the input of the OR element is connected to the second output of the mode register, the outputs of the group of which are connected to the control inputs of the strobe formation units, the second information inputs of which are the information inputs of the device group, the fourth information input of which is informational eight The first input of the mode register, the input of the delay unit is connected to the output of the reading register. 2, the apparatus according to claim 1, wherein the strobe formation unit contains two selection code registers whose inputs are the second information inputs of the block, and the outputs are connected to the first inputs of the respective comparison blocks whose second inputs are the first information input of the block three switches, the output of the first switch is the output of the block, and the information inputs are connected to the outputs of the AND element and the OR element, the first inputs of which are connected to the output of the second switch, and the second inputs to the output of the third om-- mutator data inputs of the second and third switches are connected to the outputs of the respective comparing units yu1tsie control inputs are switches by the control unit inputs .;