SU1164899A2 - Clockig device - Google Patents

Abstract

DEVICE OF TACT SYNCHRONIZATION on author. St. No. 617856, characterized in that, in order to shorten the detection time of the synchronization failures and increase the synchronization accuracy, two pulse counters and a series of subtractive blocks and a decision block are inserted, with additional outputs of the phase correction unit connected to the pulse counter inputs, and the outputs of the pulse counters connected to the corresponding inputs of the subtracting unit, the output of the decision unit is connected to the auxiliary input of the switch, the control input of the decision unit is connected to the first input of the analyzer clock sync pulses, an additional clock accumulator output is connected to the second auxiliary sync pulse analyzer input and to the first auxiliary input of the phase correction node whose second input is connected to an additional output of the discriminator, and the second output of the switch is connected to the auxiliary (A sync signal accumulator input

Description

05

.and

00

The invention relates to the transmission of discrete information, can be used in clock synchronization devices of multichannel modems with phase difference modulation and is an improvement of the invention according to the authors. St. No. 617856, The invention is to reduce the time for detecting synchronization failures and to decrease the accuracy of synchronization. Fig. I Represents the structures on the electrical circuit of the proposed clock synchronization device in Fig. 2, the decisive block is an option. The clock synchronization device contains a master oscillator 1, a phase correction section 2, a frequency divider 3 discriminator 4, a modulator control block 5, an additional divider 6 frequency, switch 7, clock analyzer 8 for clock pulses, clock signal storage device 9, modulator 10, counters P and 12 pulses, subtractive unit 3, determinant 14 of the module, decisive unit 15, G6 comparator included in the resolver unit, Ger rig 17, the counter 18 and control 19 COUNT control interval. The clock synchronization device operates as follows. Counters II, 12 pulses consider phase correction signals Addition and Subtraction, respectively, after which the counter readings are subtracted in subtractive unit 13 and module 14 determines the modulus of the difference of correction signals. In decisive block 15 it is determined whether the magnitude of the difference module exceeds the set threshold P If the threshold does not exceed, then the comparator 16 disables the monitoring mode. In this case, the decision block 15 does not provide a control signal to the switch 7. From the output of the phase correction node 2, the correction frequency f is received to the divider 3 frequencies, in which pulses of time intervals of integration, (i) storage (X), reset (C) and various decryption pulses (A) are generated every time, These pulses go to discriminator 4, synchronization drive 9 and through switch 7 to additional divider 6 frequency. The other inputs of the discriminator 4 and the accumulator 9 of the synchronization signal reach the input working signal S- through the switch 7, the discriminator 4 outputs the sign function Sing to the phase 2 correction node, by which it generates the addition pulses of the subtraction. The drive 9 of the sync signal produces a strobe on the ana-. synchronizer fault clock 8 and a desynchronization signal fed to the indication to the clock pulse analyzer 8, as well as to the phase correction section 2 for fast synchronization. If the threshold in the decision block 15 is exceeded by the modulus of the difference of the correction signals, then the comparator 16 generates a signal enabling the control mode. Trigger 17 becomes operational. From the pulses (HMV) produced by the additional frequency divider 6, the control counter 18 produces a monitoring interval, and the control interval counter 19 determines the periodicity of the cycles of the control, From the output of the decision unit 13, the control signal goes to the KONT mutator 7, which interrupts control from the frequency divider 3 for an additional frequency divider 6, and also turns off the working signal SP and connects the test signal S point to the discriminator 4 and the drive 9 of the sync signal. The test point signal is output from the analyzer output 8 faults. sync pulses. In control mode, the device operates on this signal. After conducting the monitoring cycle controlled by the L8 monitoring counter, the synchronization again returns to the operating mode with the period specified by the counter 19 of the monitoring interval. The threshold P is chosen experimentally, since it depends both on the stability (K) of the generators in the modulator and modem demodulator, and on the quality of the communication channel and the value of guard interval 1, designed to combat transients between the messages and the Group deceleration time a place in the communication channel in multichannel modems; the duration of a parcel T "is large (compared to single-channel, serial modems) and in this case is 20 ms with a guard interval of fi 3 ms; On the other hand, the level P Isit from permissible time control synchronization, i.e. from the time of keeping in phase also depending on K. t in multichannel modems it is usually more than 10 s and is practically limited by the time of control of synchronization, commensurate with the time of averaging of correction signals, i.e. within 10-20 of spreading signals. In this case, this time does not exceed 320 Cj and the threshold P is 20-30% of the number of correction signals of averaged premises. Due to the fact that a constant analysis of the situation in the communication channel was introduced, it became possible to refuse Dani's control of synchronization by cycles over the entire modem operation time, as a result of which the contradiction that was present in the prototype was resolved, which at the same time did not allow accelerating the detection of impure validity. , and improving the accuracy of description synchronization. In the proposed device, the actual control is carried out only in the event of an emergency and immediately after its occurrence. This shortens the timing of detection of synchronization failures, and the lack of a state of Monitoring during normal operation improves synchronization accuracy.

75 1 -

f

ffu & f. ongr.

P

, I iPue.S

Claims (1)

DEVICE OF TACT SYNCHRONIZATION by ed. St. No. 617856, the purpose of the failure of the pulse counter and the subtracting block and the decisive block connected in series, while to the counters inputs, which is due to the fact that, with the reduction of the synchronization detection time and the increase of the synchronization accuracy, two pulses have been introduced additional outputs of the phase correction unit are connected, and the outputs of the pulse counters are connected to the corresponding inputs of the subtracting unit, the output of the decision unit is connected to the additional input of the switch, the control input of the decision unit is combined with the first input of the analysis clock fault indicator, the additional output of the clock drive is connected to the second additional input of the clock fault analyzer and to • the first additional input of the phase correction unit, the second input of which is connected to the additional output, of the discriminator, and the second output of the switch is connected to the additional input of the clock drive ·. ·. '' L 00 with co / 1164899 2