SU1164888A1 - Converter of number of transducer to numeric code - Google Patents

Abstract

1. SENSOR NUMBER TRANSFER IN DIGITAL CODE, containing a register, informational inputs of which are connected to input buses, bit outputs are connected to inputs of a coding unit and an NAND element, the output of which is connected to the first input of the control unit and to the register control input, the installation the input of which is connected to the first output of the control unit, the second output of which is connected to the readiness bus, the second input is connected to the reset bus, and the third input is connected to the output of the matching block, the inputs of which are connected according to The inputs of the encoder, the outputs of which are connected to output buses, differ in TeMj that, in order to increase the accuracy of the conversion, a buffer storage unit is inserted into it, the information inputs and outputs of which are connected respectively to the outputs of the coding block and the inputs of the matching block, and the input the records, the control input and the readiness output of the buffer storage unit are connected respectively to the network and the fourth outputs and to (A to the fourth input of the control unit. Au 4 ;: 00 00 00

Description

2. The converter according to claim 1, оt JT and h and y and the fact that the control unit consists of a pulse shaper, the first, second and third delay elements, the inverter, the OR element and the first and second elements And, the first input control unit through a pulse generator connected in series, the first and second delay elements are connected to the first input of the control unit, the second input of which is connected to the first input of the OR element, the third

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 The input is connected to the first input. And an elet- er unit And through an inverter to the first input of the second element And, the fourth input through the third delay element connected to the second inputs of the first and second elements And, the second input of the element ShB1 connected to the output of the second element And, and the output to the fourth output of the block control the third output of which is connected to the output of the first delay element, and the second output is connected to the output of the first element I.

The invention relates to computing and can be used in multidimensional anashers for statistical analysis of angular distributions, as well as for measuring the intensity of radiation at many points in a space.

A device is known that contains a control unit, a detector number encoder, the inputs of which are connected to the input buses of the device, and the outputs are connected via a register to the output buses. .

The disadvantage of such a device is low conversion accuracy.

The closest technical solution to the invention is a sensor number to digital code converter, which contains a register, the information inputs of which are connected to INPUT-1I buses, the bit outputs are connected to the inputs of the coding unit and the NAND element, the output of which is connected to the first input of the control unit and with the register control input, the setup input of which is connected to the first output of the control unit, the second output of which is connected to the readiness bus, the second input is connected to the reset bus, and the third input is connected to the output block isolating matches, whose inputs are connected to respective inputs of an encoder, which outputs. connected to the output bus.

The disadvantage of this device is the loss of information due to

As a result, the intensity of the appearance of binary codes at the output of the device becomes less than the intensity of the input pulses, which leads to a decrease in the conversion accuracy.

The purpose of the invention is to improve the accuracy of the conversion.

The goal is achieved

The fact that the sensor number to digital code converter contains a register, the information inputs of which are connected to the input buses, the bit outputs are connected to the inputs of the coding unit and the element

AND-NOT, the output of which is connected to the first input of the control unit and to the register control input, is installed. the entrance of which is connected to

the first output of the control unit, the second output of which is connected to the readiness bus, the second input is connected to the reset bus, and the third input to the output of the matching unit, the inputs of which are connected to the corresponding inputs of the encoder, the outputs of which are connected to the output buses, is entered into a buffer storage unit informational inputs and

the outputs of which are connected respectively to the outputs of the coding unit and the inputs of the matching unit, and the recording input, the control input and the readiness output of the buffer storage unit are connected to the third and fourth outputs and to the fourth input of the control unit, respectively.

Moreover, the control unit consists of a pulse former, first,. the second and third delay elements, the inverter, the Sh1I element, and the first and second And elements, the first input of the control unit through a serially connected pulse shaper, the first and second delay elements are connected to the first output of the control unit, the second input of which is co the input element OR, the third input is connected to the first input of the first element And through the inverter to the first input of the second element And, the fourth input through the third delay element connected to the second inputs of the first and second elements And, t The input of the element OR is connected to the output of the second element AND, and the output to the fourth output of the control unit whose third output is connected to the output of the first delay element, and the second output is connected to the output of the first element I.

Figure 1 shows the functional scheme of the proposed device; figure 2 - timing diagrams illustrating his work.

The device contains (n + 1) bit register 1, the information inputs of which are connected to the corresponding input 2, the bit outputs of register 1 are connected to the inputs of: the coding unit 3, made in the form of the K-coordinate matrix, and the inputs of the element 4 AND-NOT, the output of which is connected to the first input of the control unit 5 and to the control input of the register 1, the setup input of which is connected to the first output of the control unit 5, the outputs of the coding unit 3 are connected to the corresponding inputs of the buffer storage unit 6, The outputs of which are connected to the corresponding inputs of the encoder 7 and the inputs of the matching block 8, the outputs of the encoder 7 are connected to the output buses 9, the second output of the control block 5 is connected to the readiness bar 10, and the reset terminal 1 is connected to the second input of the control block 5, the third and the fourth outputs of which are connected respectively to the recording and control inputs of the buffer storage unit 6, the control output of which is connected to the fourth input of the control unit 5, which consists of a pulse former 12, whose input is connected The first input of the block 5a is connected to the third output of the control unit 5 and to the input of the second delay element 14, the first input of the FDI element 15 is connected to the second input of the control unit 5, the second input to the output of the 16th element, And and the output is connected to the fourth output of the control unit 5, the fourth input of which through the third delay element 17 is connected to the inputs of the elements 16, 18 And, the third input of the control unit 5 is connected to another input of the 18 And element and through the inverter 19 to another input of the 16 And element .

The K-coordinate matrix of coding unit 3 is made in the form of K groups of elements 20 OR m elements each. Each of the inputs of coding unit 3 is connected to one of the inputs of one of the elements 20 OR of each group. The outputs of the elements 20 OR, belonging to the same group, form the corresponding group of outputs of the coding unit 3.

The coincidence allocation unit 8 consists of successively connected adders 21 and a comparison element 22, the other inputs of which are connected to the outputs of the register 23.

The device (3) can be used as the encoder 7, and the device (4) as the buffer storage unit.

The operation of the device will be considered for the case of use, in block 3 of the coding of the K-coordinate matrix with m 2, where a is an integer.

The device works as follows.

At a random time, one of the input buses 2 receives a pulse (Fig. 2aK. Through the input bus 2, the input signal arrives at the information input of register 1, changing the state of its first bit. At the same time, the logical output 1 (Fig. 26), arriving at the control input of the register I and blocking it. In addition, the signal from the output of element 4 does NOT enter the first input of control unit 5 and starts the driver 12, and the information from the bit outputs of the register I is fed to the inputs of the coding unit 3 and further to the inputs with The corresponding elements 20 OR, on the outputs of which the power is generated is a 1-logic-1 gate. From the outputs of the coding unit 3, the information is encoded into the information inputs of the buffer storage unit 6 (Fig. 2b). After a time sufficient for information processing by the coding unit 3 to expire The impulse of the imaging unit 12 through the delay element I 3 arrives at the output of the control unit 5 (Fig. 2d) and then to the recording input of the buffer storage unit. 6, recorded at its first address information from the outputs of coding unit 3. After that, a pulse appears at the output of the element: ha 14 of the delay coming through the output of the control unit 5 to the installation input of the register 1 (fig.2d) and establishing its initial state. Thus, in the primary transformation and registration of information in the device, only the register and blocks 3, 6 participate, which determine the inherent very small amount of the measured time. The information from the first address of the buffer storage unit 6 automatically moves to its last address, freeing up space for subsequent entries. When information simultaneously arrives at several input buses 2 (Fig. 2a, e), information about the signals registered by register 1 is again recorded at the first address of the buffer storage unit 6 and the recording made is automatically moved to its penultimate address. After the record made in the buffer storage unit 6 is moved to its last address, a pulse is produced at the output of readiness (Fig. 2g |, arriving at the input of control unit 5 and through the delay element 17 to one of the inputs of the 16.18I elements). So, the signals from the information outputs of the buffer storage unit 6 are fed to the inputs of the encoder 7, which converts them to a binary code transmitted to the output buses 9 (FIG. 2h). In addition, the information from block 6 goes to the inputs of block 8 match selection and lower order n entries combinational adders 21, resulting in a binary code (in this example, the code of the number K.), which goes to the inputs of the comparison element 22. The binary inputs of the comparison element 22 receive the binary the code of the number (K + 1), therefore at the output of the comparison element 22 in this case there is a logical 1. which enters through the input (FIG. 2 and control unit 5) (FIG. 2 - to another input of the element 13 AND, at the output of which sufficient for processing information by block 8 Coincidences appear, logical 1 arriving via the output of control unit 5 on readiness bus 10 (FIG. 2k) Thus, the analysis of information for the presence of coincidences and the formation of a binary code is carried out in a regularized flow and does not prevent the registration of information by register 1 and its initial processing. After registering a binary code with output 9, which reflects the number of the input bus 2, which received the signal by an external device, the latter sends to the reset bus 11 a pulse (Fig. 2n) arriving at the input of the control unit 5. The received pulse passes through the element 15 OR and causes the generation of a pulse at the output of the control unit 5, and the control output (, fig. 2m) of the buffer storage unit 6 is received and erases the information from its last address. At the same time, the information recorded in the buffer storage unit 6 is transferred to one address and, when the last address is filled, an impulse is formed at the readiness output (Fig. 2g) arriving at the input of the control unit 5. Information from the outputs of the buffer storage unit 6 is again fed to the inputs of the encoder 7, which converts it into a binary code arriving at the output buses 9 (Fig. 2h). If the information read from the information outputs of block 6 reflects the presence of pulses on the input buses 2, then the output of the matching selection block 8 stores logical O (Fig. 2i), which is fed through the input of control block 5 to the input of inverter 19, the logical 1 output of which arrives at one of the inputs of the 16I element. In this case, after a time sufficient for processing the information by the coincidence allotment unit 8, in the code of the delay element 17 a pulse appears through the AND element 16 and the OR element 15 OR at the output of the control unit 5 and then to the control input of the buffer storage unit 6 (Fig. 2mJ and shifting information in it. Thus, due to the absence of a signal on the readiness bus (Fig. 2k), the binary code from each code bus S is in this case The false address is not registered by the external device.

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The introduction of block 6 allows you to enter the buffering of statistical information into the conversion process itself and exclude its main component from dead time5 — the time of coincidence selection, as a result of which the device dead time becomes less than its conversion time and the registration of new information in it may begin before the end of the previous conversion cycle and generate a binary code, so that the loss of input information, which determine the error of the conversion, is. NIN, in this device is very small.

Claims (2)

1. TRANSFORMER SENSOR TO DIGITAL CODE, containing a register, the information inputs of which are connected to input buses, the bit outputs are connected to the inputs of the encoding unit and the NAND element, the output of which is connected to the first input of the control unit and to the control input of the register, the installation input of which is connected with the first output of the control unit, the second output of which is connected to the ready bus, the second input is connected to the reset bus, and the third input is to the output of the coincidence highlighting unit, the inputs of which are connected to the corresponding and the inputs of the encoder, the outputs of which are connected to the output buses, characterized in that; that, in order to increase the accuracy of the conversion, a buffer storage unit is introduced into it, the information inputs and outputs of which are connected respectively to the outputs of the coding unit and the inputs of the coincidence extraction unit, and the recording input, control input, and readiness output of the buffer storage unit are connected to the third and the fourth outputs and the fourth input of the control unit. SU ... 1164888 1 164888 2. The converter according to π. 1, based on the fact that the control unit consists of a pulse shaper, the first, second and third delay elements, an inverter, an OR element, and the first and second elements AND, the first input of the control unit through the pulse shaper connected in series, the first and second delay elements connected to the first input of the control unit, the second input of which is connected to the first input of the OR element, the third 'input is connected to the first input of the first> .go element And and through the inverter to the first input of the second element And, the fourth input is black of the third delay element connected to the second inputs of the first and second AND gates, a second input of the OR gate is connected to the output of the second AND gate and the output of the fourth output of the control unit. the third output of which is connected to the output of the first delay element, and the second output is connected to the output of the first element I. 12