SU1160413A1 - Priority device - Google Patents

Abstract

A PRIORITY DEVICE containing three OR elements, the first AND element, the NOT element, a clock generator, a counter, a code comparison scheme, the first trigger and N channels (where N is the number of sources of requests), each of which contains a trigger, the And element, and the delay element , and each channel, except the first one, also contains the second element AND on i (i 1, ..., N) inputs (where i is the channel number), the first input of the first element AND in each channel,; Connected to the corresponding information input device, the output of the first element And is connected to the S-input trigger channel, the direct output of which is connected to the input of the delay element, the output of which in the first channel is connected to the first output of the device, and in all other channels to the first input of the second element AND channel, the inverse trigger output of each i-ro channel, including the first is connected to (i 1) -th input of the second element AND of each subsequent channel, the output of the second element AND of each channel is connected to the corresponding output of the device and the input of the first OR element, the output of which is connected to the input of the element NOT and the first input of the first About element And, the second input of which is connected to the output of the clock generator, the output of the first element And is connected to the counting input of the counter, the setup input of which is connected to the output of the second element OR, the output of the counter is connected to the first input of the code comparison circuit, the second input of which is connected to the bit the device’s input, the output of the code comparison circuit is connected to the S input of the first trigger, which is connected to the output (the house of the third OR element and the second input of the second OR element, the first input of which is connected the element output is NOT, the N inputs of the third element OR are connected to the control inputs of the device and the K-inputs of the corresponding channel trigger, o: characterized in that, o in order to improve speed, 4i it additionally contains the second element AND and the second trigger, D-input CO which is connected to the inverse output of the first trigger and the first input of the second element And, the second input of which is connected to the inverse output of the second trigger, the C-input of which is connected to the output of the first element SH, and the R-input of the second trigger co Inonii yield Hilti third element, and the output of the second AND gate is coupled to second inputs of first AND gates of all the channels.

Description

This invention relates to an ultrasonic technique.

A priority device is known that contains N triggers and (N - 1) elements AND (N is the number of requests) fl

The drawback of the device is low productivity due to the implementation of the service discipline with absolute priority in it.

It is also known a priority device containing N flip-flops and (N - 1) elements AND, the inverse inputs of the flip-flops are connected to the control inputs of the device, the single output of the first trigger is connected to the first output of the device, the single trigger code of each bit starting from the second , connected to the first input of the corresponding element I, zero output of the n-th digit trigger (, ..., N-1) - to (n + 1) -th inputs of all elements And, the outputs (N - 1) elements And connected respectively to the outputs of the device from the second to the Nth, in addition, the device It contains N delay elements, N elements AND the first group of three OR elements, an inverter, a clock generator, an AND element, a counter, a code matching circuit, a trigger, the first inputs of the first group of AND elements being information inputs of the device, the second inverse inputs connected to the single output of the trigger, the outputs of each element And the first group are the single inputs of the corresponding triggers, the single output of the trigger of the first bit through the delay element and the outputs of each element And is connected to the corresponding The secondary inputs of the OR element, the output of which is connected to the inputs of the inverter and is the first input of the AND element, the second input of the AND element, is the output of the generator of contact pulses, the output of the AND element is connected to the counting input of the counter, the output of the inverter is connected to the first input of the third element OR the second input is the output of the first OR element whose inputs are the control inputs of the device, the output of the third OR element is the control input of the counter, the bit output of the counter is the first input of the matching circuit adenodes, the second input is a bit bus

setpoints from the control panel of the digital computer, the code match circuit output is connected to a single trigger input, the zero input of which is connected to the output of the first element OR C27. However, in the known device, a request for service of a new application of a higher priority, arriving before the degree of completion

the current application will reach the level

specified by the setpoint, interrupts the maintenance of the current application and proceeds to the maintenance of the new one. This leads to the possibility of a large

the number of unserved services and, accordingly, an increase in the overhead of machine time and a decrease in the productivity of the organization. At the same time, information may be lost, since interrupted information is not always saved in external devices.

The purpose of the invention is to increase productivity and speed.

devices by changing the discipline of interruption.

The goal is achieved by the fact that a priority device containing three elements OR, the first

AND element, NOT element, clock generator, counter, code comparison scheme, first trigger and N channels (where N is the number of sources of requests), each of which contains a trigger, AND element, element

delays, and each channel, except the first, contains the second element And on the i (i 1, ..., N) inputs (where i is the channel number), with the first input

The first element And in each channel is connected to the corresponding information input, the device, the output of the first element And is connected to the S-BXO channel trigger channel, direct output

which is connected to the input of the delay element, the output of which in the first channel is connected to the first output of the device, and in all other channels to the first input of the second element AND of the channel, while the inverse output of the trigger of each i-ro channel, including the first, is connected to (i 1) th input of the second element And each subsequent channel,

the output of the second element AND of each channel is connected to the corresponding output of the device and the input of the first, OR element, the output of which is connected to the input of the element NOT and the first input of the first element AND, the second input of which is connected to the output of the clock generator, the first element AND is connected to the counting input of the counter , the installation input of which is connected to the output of the second OR element, the output of the counter is connected to the first input of the comparison circuit, the second input of which is connected to the discharge input of the device setpoint, the output of the comparison circuit The codes are connected to the S-input of the first trigger, the R-input of which is connected to the output of the third OR element and the second input of the second OR element, the first input of which is connected to the output of the NO element, and the N inputs of the third OR element are connected to the control inputs of the device and R -inputs of the corresponding channel triggers, additionally contains the second element And the second trigger, the D input of which is connected to the inverse output of the first trigger and the first input of the second element And, the second input of which is connected to the inverse output of the second trigger ra, C-terminal to torogo connected to the output of the first OR gate, the R-input of the second flip-flop connected to the output treteg OR gate and the output of the second AND element is connected to second inputs of first AND gates of all the channels. The drawing shows the functional scheme of the device. The device contains channels 1, triggers 2, delay elements 3, elements AND 4 and 5, element 6, generator 7 clocks, element 8, counter 9, code comparison circuit 10, trigger 11, elements OR 12-14, information inputs 15, the control inputs 16, the outputs 17, the setpoint code input 18, the trigger 19 and the AND 20 element. The device operates as follows. Information inputs 15 receive requests for servicing external devices. Query priorities clever

increase with the channel number. The request with the highest priority blocks the rest of the requests using AND 4 elements.

In the initial state, on the direct outputs of the flip-flops 2 of all channels 1, the trigger 11 of the device and the D-flip-flop 19 are zero potential, all bits

The scientific research institute prohibits the operation of the elements of And 5, preventing any applications for service, including applications with a priority higher than the priority serviced.

Previously, the received application is serviced to the end regardless of the input to the requests. 134 counters 9 zeroed. The tO code comparison circuit on bit input 18 from the computer control panel is given a Setpoint signal in the form of a binary: code corresponding to the upper level limit in a time or percentage scale, the achievement of which is performed by the current program (solved task) until complete completion and can not be interrupted by a higher priority request. When a service request is received on one of the information inputs 15 through the element 5, the trigger 2 of the corresponding channel is activated, and in the code 17 a signal is triggered, initiating the maintenance of the request. With the inverse output of the trigger 2, a signal of the prohibition on the first elements AND 4 of the subsequent (low priority) channels is received. The signal at the output 17 of channel 1, which received the service request, passed through the third element OR 14, goes to the element NOT 6, from the output of which the zero potential Passes through the element OR 12 and goes to the installation input of the counter 9, removing the single reset signal, acting at counter 9 in the absence of requests, preparing it to receive clock pulses. In addition, a single potential from the element b terminal OR 14 enters the first input of element 8, allowing the clock pulses to pass from the generator of 7-stroke pulses to the input of counter 9. As the application is serviced, counter 9 counts the clock pulses, and its content is constantly compared with binary setpoint code using a 10 kd circuit. If the code in counter 9 coincides with the setpoint code, the signal from the output of circuit 10 cocks trigger 11, as a result of which its inverse output produces a logical O, which closes AND 20 element. Consequently, if the service request for the second application enters the device. the degree of completion of the current application reaches the level specified by the setpoint, then, in the corresponding channel of channel 1, element 5 is triggered, which triggers the corresponding trigger 2, the latter sends a signal to prohibit elements 4 of all channels with a lower priority. As a result, at the output of the element OR 14, a difference is generated between logical 1 and logical O, which triggers trigger 19, at the inverse output of which logical o, blocking element AND 20 at the second input and then all elements 5 occur, eliminating thereby service rates, including applications with a priority higher than the priority served, and the second application is always served to the end. Thus, if the priority of the second application is higher than the priority of the current 4136, the signal at the corresponding output 17 is removed, the service of the current application is terminated and the service of the second application is started, until the end of which the entry into service of any application is prohibited. with higher priority. After the request is completed, the response signal to one of the control inputs 16 of the device resets trigger 2 of the corresponding channel 1, as well as triggers 11 and 19 (from the OR element 13). At the same time, the prohibition of the second inputs of the second elements of AND 5 is lifted. Thus, in the proposed device, unlike the known number of orders interrupted before the end of service, is limited to one J, which reduces the overhead of machine time and increases the device performance by reducing the average time service.

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Claims (1)

PRIORITY DEVICE containing three OR elements, the first AND element, the NOT element, the clock, counter, code comparison circuit, the first trigger and N channels (where N is the number of query sources), each of which contains a trigger, an And element, a delay element, and each channel, except the first, also contains a second And element at i (ί = 1, ..., N) inputs ( where i is the channel number), and the first input of the first AND element in each channel is connected to the corresponding information input of the device, the output of the first AND element is connected to the S-input of the channel trigger, the direct output of which is connected to the input of the delay element, the output of which is in the first channel connected to the first output of the device, and in all other channels - with the first input of the second element of the channel AND, while the in-1 version of the trigger output of each £ -th channel, including the first, is connected to the (i + 1) ~ m input of the second element And of each subsequent channel, the output of the second element And of each channel is connected to the corresponding output of the device and the input of the first OR element, the output of which is connected to the input of the element NOT and the first input of the first element AND, the second input of which is connected to the output of the clock generator, the output of the first element And is connected to the counting input of the counter, the installation input of which connected to the output of the second OR element, the output of the counter is connected to the first input of the code comparison circuit, the second input of which is connected to the discharge input of the setpoint of the device, the output of the code comparison circuit is connected to the S-input of the first trigger, whose R input is connected to the output of the third OR element and the second input of the second OR element, the first input of which is connected to the output of the NOT element, and N inputs of the third OR element are connected to the control inputs of the device and the R-inputs of the triggers of the corresponding channel, characterized in that, with To improve performance, it additionally contains a second element And and a second trigger, the D-input of which is connected to the inverse output of the first trigger and the first input of the second element And, the second input of which is connected to the inverse output of the second trigger, the C-input of which is connected to the output of the first element OR, and the R-input of the second trigger is connected to the output of the third OR element, and the output of the second AND element is connected to the second inputs of the first AND elements of all channels.