SU1140123A1 - Signature analyser - Google Patents

Abstract

1. A SIGNATURE ANALYZER containing a pulse generator, a shift register, a modulo two adder, a strobe driver and a display unit, wherein the outputs of the shift register are connected respectively to a group of inputs of a modulo two adder, in order to expand the range of use by providing software control intervals, the first and second multiplexers, the first, second and third elements AND, the address setting block, the switch, the element OR, the element 2И-ШШ, the first and second switches The operation mode and the associative memory block, whose outputs are connected to the first group of information inputs of the first multiplexer, the second group of information inputs of which are connected to the Start and Stop inputs, the outputs of the first multiplexer are connected to the Start and Stop inputs of the gateway-strobe, the output of which is connected to the first direct input of the first element AND, the second direct input of which is the synchronization input of the device, the output of the first element AND is connected to the first input of the OR element, the output of which is connected with the shift register synchronization input, the reset input of which is connected to the reset input of the gate generator and the initial setup input of the arrangement, the register, shift outputs are connected respectively to the inputs of the display unit and the first group of information inputs of the second multiplexer, the control input of the first multiplexer is connected to the movable contact of the first switch mode operation, closing and razmikyu con (L clocks which are connected to the tires of zero and single potential, respectively, information input The device is connected to the first disconnecting contact of the second operating mode switch, the first movable contact of which is connected to the input of the modulo two adder and the first information input of element 2И-Ш1И, the output of which is connected to the information input of the shift register; the first output of the address setting block is connected to the first I close by a single contact of the second mode switch, the second output of the address setting block is connected to the second input of the OR element, the third input of which is connected to the output of the second element, And my input is connected to the output of the pulse generator, the opening and closing contacts of the switch are connected to the buses of a single and zero potential

Description

accordingly, the movable contact of the switch is connected to the inverse input of the second element And, the first input of the third element And and the first control input of the associative memory block, the second movable contact of the second operation mode switch is connected to the second input of the third element And, the inverse input of the first element And, the second multiplexer and the second control input of the associative memory block, the comparison inputs of which are connected to the outputs of the second multiplexer, the output of the third element I is connected to direct and inverse control inputs of the element 2И-OR, the second information input of which is connected to the output of the modulo two adder, the second breaker and the second end contact of the second switch are connected to the buses of zero unit potential, the second group of information inputs of the second multiplexer are address inputs devices. .

2, the analyzer according to claim 1, wherein the associative memory unit contains the first and second operational memory units.

40123

two elements, an OR element and two switches, the comparison inputs of the associative memory block are connected respectively to the dead-H inputs of the first and second RAM blocks, whose outputs are the outputs of the associative memory block, the first control input of which is connected with the inverse input of the OR element, the output of which is connected to the first inputs of the first and second elements of NAND, the second control input of the associative memory unit is connected to the second inputs of the first and second elements of NAND, the outputs of which are The first and second RAM blocks are input pockets, respectively, the information inputs of which are connected to the direct input of the OR element and the moving contact of the first switch, the opening and closing contacts of which are connected to the zero and single potential buses, respectively, the inverse and the third direct inputs of the first and the second elements AND-NOT, respectively, are connected to the closing contact of the second switch, the movable contact of which is connected to the zero potential bus,

The invention relates to computing and can be used to monitor and diagnose digital devices for various purposes using the method of signature analysis.

A device for controlling discrete objects is known, comprising a contact block, two analog-digital converters, three registers, a switch, a selector, a gate driver, a memory block, a poll generator, a decoder, a signature comparator, and an indicator ij.

Closest to the proposed by the technical nature of the signature analyzer, containing a shift register with feedback through a modulo two adder, a test driver, a gate driver, two buffer registers, a memory unit, a polling pulse generator, a decoder, a comparator and a display unit, the input of the buffer register is the information input of the device, the start and stop inputs and the clock input of which are connected to the first, second and third inputs of the strobe generator, respectively, the output of the first buffer register connected to the input of an adder modulo two, the output of which is connected to the information input of the shift register, the outputs of which are connected to the information inputs of the second buffer register, the output of the strobe generator is connected to the first input of the display unit and the clock inputs of the shift register and the second buffer register whose outputs are connected to the information inputs of the memory block, the first group of 3 information inputs of the comparator on the inputs of the decoder, the outputs of which are connected to the group of inputs of the display unit, the second input to The second is connected to the comparator output, the outputs of the memory block are connected to the second group of information inputs of the comparator, the control input of which and the write-read input of the memory block are connected to the first output of the polling pulse generator, the second output of which is connected to the clock input of the second buffer Register A disadvantage of the known devices is the limited scope due to the lack of the possibility of programmatically setting consoles. The purpose of the invention is to expand the scope of use of the signature analyzer by providing the programmed setting of control intervals. The goal is achieved in that a signature analyzer comprising a pulse generator, a shift register, a modulo two adder, a strobe driver and a display unit, wherein the outputs of the shift register are connected respectively to the group of inputs of the modulo two adder, the first and second multiplexers, the first, the second and third elements AND, the address setting block, the switch, the OR element, the element 2И-OR, the first and second switches relativity of work and the block of associative memory, the outputs of which are connected to the first group of information the first multiplexer inputs; the second group of information inputs of which are connected to the Start and Stop inputs; the outputs of the first multiplexer are connected to the Start and Stop inputs of the gate generator; the output is connected to the first direct input of the first element AND, the second direct input is the device synchronization input , the output of the first element And is connected to the first input of the OR element, the output of which is connected to the synchronization input of the shift register, the reset input of which is connected to the reset input of the former both of them are connected to the inputs of the display unit and the first group of information inputs, the second multiplexer, the control input of the first multiplexer is connected to the moving contact of the first operation mode switch, the closing and opening contacts of which are connected to the buses a zero and a single potential, respectively, the information input of the device is connected to the first break contact of the second mode selector switch, the first mobile The first contact of which is connected to the input of a modulo-two adder and the first information input of the element 2И-Ш1И, the output of which is connected to the information input of the shift register, the first output of the address setting unit is connected to the first closing contact of the second operation mode switch, the second output of the setting unit address is connected to the second input of the SHS element, the third input of which is connected to the output of the second element I, the direct input of which is connected to the output of the pulse generator, opening and closing the contacts of the switch They are connected to the buses of single and zero potentials, respectively, the movable contact of the switch is connected to the inverse input of the second element And, the first input of the third element And and the first control input of the associative memory unit, the second moving contact of the second mode switch And, the inverse input of the first element AND, the control input of the second multiplexer, and the second control input of the associative memory block, the comparison inputs of which are connected to the outputs of the second multi Iplexer, the output of the third element And is connected to the direct and inverse control inputs of the element 2I-Sh1I, the second information input of which is connected to the output of the modulo two adder, the second disconnecting and second closing contacts of the second switch are connected to the buses of zero and one potential, respectively, the second the group of information inputs of the second multiplexer is the address inputs of the device. In addition, the associative memory block contains the first and second RAM blocks, two AND 51NO elements, the OR element and two switches, and the comparison inputs of the associative memory block are connected respectively to the address inputs of the nerve and the second RAM blocks, the outputs of which are the outputs of the associative memory block, the first control input of which is connected to the inverse input of the OR element, the output of which is connected to the first inputs of the first and second elements of NAND, the second control input of the association block the memory is connected to the second inputs of the first and second NAND elements, the outputs of which are connected to the write-read inputs of the first and second blocks of RAM, respectively, whose information inputs are connected to the direct input of the SHS element and the movable contact of the first switch {Open and the contacting contacts of which are connected to the tires of zero and unit potential, respectively, the inverse and the third direct inputs of the first and second elements AND –NE, respectively, are connected to the closing contact of the second switch chatel, the movable contact of which is connected to the zero potential bus. FIG. 1 shows a signature diagram of the signature analyzer; in fig. 2 and 3 are examples of the implementation of schemes for specifying addresses and an associative memory block. The device contains a pulse generator 1, an address setting block 2, a shift register 3, an indication block 4, an associative memory block 5, a gate driver 6, multiplexers 7 and 8, an adder 9 modulo two, elements 10-10, elements OR 13, an element 2I-OR 14, switch 15, switches 16 and 17 of the mode of operation input 18 of the initial installation, input 19 synchronization, input 20 Start, input 21 Stop, information input 22 and address inputs 23. The block of addresses and addresses consists of triggers 24 and 25 , element ШШ 26, element 27 for delay and buttons 28 and 29 The block of associative memory contains a block 31 and 30, and RAM memory, the AND-NO element 32 and 33, an OR gate 3 of the switch button 35 and the switch 36. It should be proposed device operates properly. 36 There are two modes of its operation, in the first of which the beginning and end of the measuring interval are set by the control signals Start and Stop, coming to the inputs 20 and 21 of the device, and in the second border of the measuring interval are set by n-bit addresses of the beginning and end of the program segment, served on address inputs. 23. According to the signal from the device input 18, the initial setting of the gate generator 6 and the shift register 3 is carried out. Consider the first mode of operation of the device. In this case, the switch of mode 16 ra: bots is set to the position in which the potential input to the control input of multiplexer 7 provides the passage to its output of signals from the inputs 20 and 21 of the device. The switch 17 is set to a position in which from its second contact group, the inputs of the elements 10 and 12 and the control input of the multiplexer 8 are supplied with a zero potential. The Start signal from the device input 20 is fed through multiplexer 7 to the input of the gate driver 6, the output of which establishes a single potential and through the elements 10 and III 13 to the C input of the shift register 3 the clock pulses from the device 19. When connected to the information input 22 of the signature analyzer of the monitored data stream, it passes through the first contact group of the switch 17 to the input of the adder 9 modulo two, which, together with the shift register 3, forms a linear recurrent sequence generator of the maximum period, generating a binary period of the period M 2-1. From the output of the 3 shift register, the n-bit code (signature) enters. block 4, where it is displayed (usually with a four-bit hexadecimal display) For comparison with a reference code. In the second mode of operation of the signature analyzer, the switch 16 is set to a position in which signals from the output of the block 5 of the associative memory pass through multiplexer 7. In this mode, the work cycle is divided into three phases: erasing the previously recorded addresses of the beginning and end and the measuring interval; recording addresses of the beginning and end of the controlled program segment; data control The first two phases relate to preparatory operations, conventionally called programming, and the third phase is working. The specified phases are set by the position of the switch 17. In the first two phases of operation, the inverse input of the element 10 receives a forbidding single potential, and the multiplexer 8 sends information from the output of the 3 shift register to the comparison inputs of the associative memory 5, and FDI 14 and OR 13 to the D- and C-inputs of the shift register 3, respectively, information from the outputs of the address setting block is received. Erasing previously recorded addresses to the beginning or end of the measuring interval is performed as follows. If on the display of block 4 it indicates with a null signature, then before deleting one must be written into register 3 at least one unit. This is ensured by pressing button 28 of block 2 once. Pressing button 28 from the output Q of trigger 24 sends a single signal to the information input of the 3 shift register through the 2I-OR 14 element. Moreover, from the rycode Q of the trigger 24 through the OR element 26 and delay element 27 The first output of block 2 is a signal that passes through the OR 13 element to the clock input of shift register 3. The delay is necessary to increase the reliability of writing codes to the register3. If the signature is different from zero, then it is necessary to switch the switch 15 to the position where the signal from the output of the element 12 to the inverse control input of the element 2I-OR 14 receives a signal allowing the signals from the output of the adder 9 to pass through modulo two. Since the zero potential arrives at the input of the adder 9 from the second output of block 2. a linear recurrent sequence of the period M 2-1 65535 is generated. To increase the rate of formation of the sequence, pulses of about 100 kHz from the generator 1 output pass through the synchronization register of the shift register 3 11 and the element OR 13 “Therefore, it is sufficient to hold switch 15 in this position for about 1 s. The signals from the output of the shift register 3 through multiplexer 8 are fed to the inputs of block 5 of associative memory, which are the address inputs of blocks 30 and 31. In accordance with the law of formation of linear recurrent sequences, in this order, in some order, all N-bit addresses are searched, except addresses 00 ... 00. At the information inputs of blocks 30 and 31 there is a zero signal, since button 35 is pressed. When the signal O comes from the contacts of the switch 15 to the first control input of the unit 5, a single signal appears at the first inputs of the AND 32 and 33 elements through the OR 34 element. The inputs of these elements receive a single potential from the second control input of block 5. Depending on the position of the switch 36 of the control starting and ending addresses, the resolving potential is fed to the third input of one of the AND-NE elements 32 or 33, and correspondingly corresponding to the recording information, passes to the write-read inputs of the corresponding block 30 or 31 of the RAM. Thus, O is recorded in all cells of the block 30 or 31 selected by the switch 36, except for the cell with the address 00 ... 00. In order to erase the contents of this cell at the same time as pressing the PR 15 switch, it is necessary to input a setup signal to input 18. The shift register 3 is then set to the state 00 ... 00 and this code passes to the inputs of block 5. The information in block 5 is erased. The entry in the memory of the addresses of the beginning and end of the monitored program segment is performed as follows. First, the address code is dialed sequentially, bitwise starting from the higher bits, by successively pressing buttons IV and 29 of block 2. JIpH this potential, corresponding to the discharge level, is set at the second output of block 2, and on the first BOM of its output after each pressing of any button with some delay, a shear pulse appears. The signals from the outputs of block 2 through the element 2I-OR 14 and the element OR 13 passes to the D- and C-inputs of the register 3 shift. The process of dialing and writing it to register 3 is monitored by the indicator unit 4,, In the position of the switch 17 corresponding to the phase of the so-called programming, the outputs of the shift register 3 through multiplexer 8 are connected to the inputs of the block 5. Let the switch 36 of this block be set to when the permitting potential arrives at the third input of the NAND 32, and the third input of the NE-33 is forbidden, because of the potential corresponding to the reading of information at the write-read input of the block 30, When you press ki 35 block 5 to the information inputs of blocks 30 and 31 receives a single potential. At the same time, the signal corresponding to the write mode enters the write-read input of block 30 through the OR 34 element and the NAND-32 element, and the cell records the address of the end address of the measurement interval into the cell whose address is in register 3 of the shift. . In this case, the switch 36 of block 5 must be set to the position when the permitting potential is supplied to the third input of the element AND-NOT 3, and the input is denied to the input of the element AND-NOT 32. In block 31 1, several cells can be written, which corresponds to several addresses end of measurement interval for programs that have a branch. When monitoring the data flow, the switch 17 is set to the position corresponding to the operating phase of the mode. At the same time, the address inputs of the device are connected to the output of the multiplexer 8, a zero potential is supplied to the inverted input 2310 of the And 10 element, and data from the information input 22 of the device through the adder 9 modulo two I-element 2И-ШИИИ 14 to the D input of the shift register 3. The inputs of the read-write blocks 30 and 31 receives the potential corresponding to the read information. As long as the current address is not equal to the addresses at which 1 was recorded in blocks 30 and 31, zero signals are present at their outputs. As soon as the current address is compared with the address at which 1 is recorded in block 30, a single signal appears at its output, which through multiplexer 7 enters the input of the former 6 as the control signal of the beginning of the measuring strobe. Similarly, when reading information from block 31, a single signal of the end of the measuring interval appears at which the output of the imaging unit 6, and therefore the element 10, is set to zero potential and the input to the C input of the register 3 of the shift pulses stops the gate driver 6 can be used, for example, an RS flip-flop. Otherwise, the operation of the signature analyzer in this mode does not differ from the operation when specifying the measurement interval with external control signals. The inputs (informational and synchronization) of the signature analyzer are connected to the corresponding points of the monitored device. Thus, in the proposed device, it is possible to set the measurement interval not only with external control signals, but also with the addresses of the beginning and end of the program segments, which expands the scope and effectiveness of the signature analyzer, since it is suitable for testing hardware-software systems without their modification.

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Claims (2)

1. A SIGNATURE ANALYZER containing a pulse generator, a shift register, an adder modulo two, a gate generator and a display unit, the outputs of the shift register being connected respectively to a group of inputs of an adder modulo two, characterized in that, in order to expand the scope of use by providing software setting control intervals, the first and second multiplexers, the first, second and third AND elements, the address setting unit, the switch, the OR element, the 2-OR element, the first and second mode switches are introduced into it operation and an associative memory unit whose outputs are connected to the first group of information inputs of the first multiplexer, the second group of information inputs of which are connected to the Start and Stop inputs of the device, the outputs of the first multiplexer are connected to the Start and Stop inputs of the gate generator, the output of which is connected to the first direct input of the the first AND element, the second direct input of which is the synchronization input of the device, the output of the first AND element is connected to the first input of the OR element, the output of which is connected to the sync input the shift register, the reset input of which is connected to the reset input of the gate driver and the input of the initial installation of the device, the outputs of the shift register are connected respectively to the inputs of the display unit and the first group of information inputs of the second multiplexer, the control input of the first multiplexer is connected to the movable contact of the first operating mode switch, the make and break contacts of which are connected to the buses of zero and unit potential, respectively, the information input of the device is connected to by the first disconnecting contact of the second operating mode switch, the first movable contact of which is connected modulo two to the adder input, and the first information input of the II-OR element, the output of which is connected to the information of the shift register, the first output of the address setting unit is connected to the first closing contact of the second switch operation mode, the second output of the address setting unit is connected to the second input of the OR element, the third input of which is connected to the output of the second AND element, the direct input of which is connected to the output pulse generator, the opening and closing contacts of the switch are connected to the buses of unit and zero potential, respectively, the movable “contact of the switch is connected to the inverse input of the second element And, the first input of the third element And and the first control input of the associative memory block, the second movable contact of the second mode switch is connected with the second input of the third AND element, the inverse input of the first AND element, the control input of the second multiplexer and the second control input of the assoc memory, the comparison inputs of which are connected to the outputs of the second multiplexer, the output of the third element And is connected to the direct and inverse control inputs of the 2I-OR element, the second information input of which is connected to the output of the adder modulo two, the second NC and the second NO contacts of the second switch are connected to buses of zero unit potential, respectively, the second group of information inputs of the second multiplexer are the address inputs of the device. . 2. The analyzer according to claim 1, characterized in that the associative memory block contains the first and second random access memory blocks, two NAND elements, an OR element, and two switches, the comparison inputs of the associative memory block being connected respectively to the address inputs of the first and second RAM blocks, the outputs of which are the outputs of the associative block of memory, the first control input of which is connected to the inverse input of the OR element, the output of which is connected to the first inputs of the first and second elements AND NOT, the second control the first input of the associative memory block is connected to the second inputs of the first and second AND-NOT elements, the outputs of which are connected to the recording inputs of the first and second RAM blocks, respectively, the information inputs of which are connected to the direct input of the OR element and the movable contact of the first switch, opening and closing contacts which are connected to the buses of zero and unit potential, respectively, the inverse and third direct inputs of the first and second elements AND are NOT connected respectively to the make contact ohm of the second switch, the movable contact of which is connected to the bus of zero potential.