SU1134964A1 - Device for programming integrated circuits of read-only memory - Google Patents

Abstract

A DEVICE FOR PROGRAMMING MICROSHEMES OF CONSTANT MEMORY, containing the first, second and third pulse shapers, the inputs of the first groups of which are connected to the information buses, the inputs of the second groups are connected to the control buses, the outputs of the first, second and third pulse shapers are connected to the inputs of the first, the second and third power amplifiers, the outputs of the first and second power amplifiers are respectively the first and second control outputs of the device, the output of the third power amplifier is connected to the power input of the key block, whose outputs are connected to the inputs of the first group of the control unit and are the numerical outputs of the device, the inputs of the second group of the control unit are connected to the outputs of the first register and the inputs of the first group of the key block, the inputs of the third group of the control unit are connected to the source the reference voltages, the information inputs of the first, second, and third registers are connected to the information buses, and the 5 master inputs are connected to the control buses, the outputs of the second register are connected to the second inputs The third group of the key block, the outputs of the third register are address outputs of the device, characterized in that, in order to expand the field of application of the device by increasing the class of programmable chips, it contains the first, second and third pulse edge drivers, the fourth and fifth registers, the block comparison, synchronization unit, amplifier-transmitter, efforts (L-receiver and digital-analog converter, information inputs of the fourth and fifth registers and § outputs of the amplifier-receiver are connected to the information Nyo4I tires, the outputs of the fourth register are connected to the information and control inputs of pulse formers, the outputs of which are connected to the inputs of the corresponding power amplifiers, and the outputs of the third pulse generator are connected to inputs 4 of the third group of key block, control inputs the fourth and fifth registers and the outputs of the synchronization unit are connected to the control buses, the outputs of the fifth register are connected to the inputs of the digital-to-analog converter, the output of which is connected to the fifth input of the block ka comparison, BToposi. the third and fourth inputs of which are connected to the outputs of the respective power amplifiers, the outputs of the comparison unit and the outputs of the unit

Description

the control is connected to the corresponding inputs of the amplifier-transmitter, whose outputs are connected to the inputs of the first group of the synchronization unit and the inputs of the amplifier-receiver, the control input of the amplifier-transmitter 1 134964 is connected to the control output of the synchronization unit, the inputs-outputs of the first, second and third groups which are the control inputs-outputs of the first, second and third groups of the device, respectively.

The invention relates to computing technology, in particular to computer controlled control devices of programming, and can be used in programming of memory microchips. A device for programing microcircuits of a fixed memory is known, which is a programming board that is connected via buffer registers to the controller, which contains a control unit, a power supply unit, a power supply switch, auxiliary circuits tj. This device differs in simplicity, but is characterized by low productivity, inability to generate pulse sequences of various shapes, which is necessary to increase the reliability of recording when switching from programming one type of chip to another. The closest in technical essence and circuit design to the proposed device is. Programming Chips of the Permanent Memory, consisting of a software control unit, a interface unit with external I / O devices information programming board 2J. However, the known device is characterized by unnecessary complexity, which is associated with the presence of a standalone software control device and interface block. In most cases, these units can be replaced by serially running mini- and microcomputers, for example, Electronics series, with peripheral equipment and sophisticated mathematical software. In such cases, it is convenient to have only a chip programming device — a programming board containing the necessary hardware means for generating programming pulses. However, in a known device, a programming board is not only structurally, but also cannot be functionally integrated so that it can be easily connected to a computer, moreover, it does not have the ability to change the duration of the fronts of programmable pulses that are different for different types of programmable chips. , significantly reduces the scope of such a device. The purpose of the invention is to expand the field of application of the device due to the magnitude of the class of programmable chips. The goal is achieved by the fact that a device for programming a fixed memory chip containing the first, second and third pulse shapers, inputs whose first groups are connected to information buses, the inputs of the second groups are connected to control buses, the outputs of the first, second and third drivers the pulses are connected respectively to the inputs of the first, second and third power amplifiers, the outputs of the first and second power amplifiers are respectively the first and second control codes of the device Twa, the third power amplifier output is connected to the input of the power key block, whose outputs are connected to inputs of the first group and the control unit are numerical The yields. By the device, the inputs of the second group of the control unit are connected to the outputs of the first register and. the inputs of the first group of the key block, the inputs of the third group of the control block are connected to a non-reference point of the reference voltages; the information inputs of the first, second and third registers are connected to information plans, and the control inputs are connected to the control buses, the outputs of the second register are connected to the inputs of the second group the keys, the outputs of the third register are the address outputs of the device, contains the first, second and third pulse edge generators, the fourth and fifth registers, the compare block, the synchronization unit, the amplifier the receiver, the amplifier-receiver and the cy-analog converter, the information inputs of the fourth and fifth registers and the outputs of the amplifier-receiver are connected to the information buses, the outputs of the fourth register are connected to the information and control of the inputs of the pulse front drivers, the outputs of which are connected The inputs of the corresponding power amplifiers, the outputs of the third pulse generator are connected to the inputs of the third group of the key block, the control inputs of the fourth and fifth registers, and the outputs of the synchronization block with They are connected to control buses, the outputs of the fifth register are connected to the inputs of a digital-analog converter, the output of which is connected to the first input of the comparison unit, the second, third and fourth inputs of which are connected to the outputs of the corresponding power amplifiers, the outputs of the comparison unit and the outputs of the control unit connected to the corresponding inputs of the amplifier-transmitter, the outputs of which are connected to the inputs of the first group of the synchronization unit and the inputs of the amplifier-receiver, the control input of the amplifier-controller is connected to the control In the output of the synchronization unit, the outputs of the first, second and third groups of which are the control inputs-outputs of the first, second and third groups of the device, respectively. Fig. 1 shows the block diagram of the proposed device J in Fig. 2, the functional diagram of the synchronization unit when the device is connected to the CM AJ in Fig. 3 is the functional diagram of the synchronization unit that can be used for the ka-60 microcomputer. The device (FIG. 1) contains the first 1, second 2 and third 3 pulse shapers, information buses 4, control buses 5, first 6, second 7 and third 8 power amplifiers, first 9 and second 10 control outputs of the device, block 11 keys, control unit 12, numerical outputs 13 of the device, first register 14, reference voltage source 15, second 16 and third 17 registers, device address outputs 18, first 19, second 20 and third 21 form. The pulse fronts, the fourth 22 and the fifth 23 registers, the comparison unit 24, the amplifier-receiver 25 and the transmitter 26, the digital-to-analog converter 27, the synchronization block 28, the voltage converter 29, power supply control terminal 30, inputs - outputs of the first 31, second 32 and third 33 device groups, connector 34 for installing programmable microchips, buffer register 35, intermediate register 36, digital-to-analog converter 37, key block 38, capacitor block 39, switch block 40. Block 28 (FIG. 2) contains a decoder 41, inverters 42, 43 and 44, block 45 of elements I, element I 46, element 47 delay and amplifier 48. Tires 31, 32 and 33 are connected to the data buses, addresses and computer control respectively . The unit works as follows. In the recording mode, the control bus 33 receives the signals and prohibits the operation of the element 46 and enables the operation of the elements I of block 45. The address of the corresponding device register enters the bus 32 and is converted into a unitary code using the decoder 41 into the block 45 of the elements. After the HSS signal is available, a corresponding control signal is provided to the control bus 5. the same signal after passing through the delay element 47 and the bus distributor 48 is fed to the input from the computer of the CI. The data on bus 1 is received through the amplifier-receiver 25 to the inputs of registers and recorded in the register that is built by the signal from bus 5. In the read mode, the control bus receives signals that close the block of the E-elements 45 and allow the operation of the E-46o element. This element is opened by the amplifier-transmitter 26, and information is supplied via bus 31 to the EV. The functional circuit of the synchronization unit (Fig „3) can be used when connected to the electronic computer Electronics-60" Block 28 contains an external device selection circuit 49 And 50 ,, rigger 51, register 5 decoder 53, elements AND 54, 55, 56 and 57, decoder 58, element OR 59s element AND 60, element 61 delay, amplifier 62. The micro-computer has a combined multiplexed address and data bus 31 and bus 33 Controls By the control limit 33, the signals VUN, SIAN, SIPN, BYTE, INPUT N, OUTPUT N, RESET H are received, which allow organizing the transfer direction and synchronization of overfills in the system. The unit works as follows. The exchange operation with the programming device begins with the input & chi addresses on the bus 31 and the signal VUN. The most significant bits of the address code go to circuit 49, where they are fixed and recorded through element E 50 and recorded with the front of the signal SIAN, Odkoveremenno, the lower order bits of the address are fixed with the same signal in register 52. Thus, the trigger 51 records the sign of accessing the programmers {world, and in register 52, the address of the register to which the access occurs. The minor address bits are sent to the decoders 53 and 58, which are controlled by AND 54 57 elements. This allows for single-byte or layer-by-layer data exchange depending on the BYTE signal and the low-order bit address. The operation of the elements of And 56 and 57, and therefore the decoders 53 and 58, is carried out by a signal from trigger 51. The outputs of the decoder form the programming device control bus 5 and the read signal going to block 26. Organizing the asynchronous exchange between the microcomputer and the programming device is carried out by the signals O, N, IN, AND, and SIPN by means of the elements OR 59, And 60, the delay element 61 and the amplifier 62, as when using a CM-4 computer. The resetting of the interface block is accomplished by the RESET N signal, by zeroing the trigger 51. The device operates as follows. Preparatory mode. In this mode, the selected mini or micro computer is connected via detachable connections to a chip programmer. At the same time, information, address and control buses of the selected mini- or microcomputer are connected respectively to the control inputs of the first 31, second 32; the third 33 groups of programming devices. The required input voltage is supplied to the power inlet 30. After the Programming Device is docked with the computer and supplied with power 1e, the voltage can be transferred to the next mode. Setting mode. In this mode, the amplitudes of the programmers and the signals produced by the shaper 1, 2, and 3 pulses are calibrated, and the edges of the programming pulses are set in accordance with the requirements. no technical specifications for the programmable chip type. The calibration of the amplitudes of the programming pulses is carried out as follows. A precision digital-to-analog converter (D / A converter) 27 (for example, 572 PA 1) and a comparison unit 24 are introduced into the circuit. Since for each type of programmable microcircuit the required pulse parameters are known, a binary code corresponding to the value of the required output voltage is written to the register 23. At the output of the D / A converter, the required voltage is set with a given accuracy. Then age- or descending codes are successively applied to the buffer 35 and further to the intermediate 36 registers of drivers of 1, 2 and 3 pulses. These codes are sent to the corresponding D / A pulse shaper. At its output, the voltage will vary. The output voltages from the corresponding DACs through the power amplifiers 6 (7.8) are fed to the inputs of the comparator unit 24, which determines the moment of the comparison of the voltage from the pulse generator with the exact value received from the DAC 27. The code corresponding to the required output voltage shaper 6 (7, 8) pulses, is recorded in the memory of amendments, which is allocated to the computer memory. Thus, for all required values of the output voltage (in those cases, when it is stepped) and for all three channels, the codes are sequentially determined, which in the process of operation go to the registers 35 of the formers of 1, 2 and 3 pulses. Such an organization makes it possible to simplify the D / A converter 37 of the pulse shaper, to achieve its high speed and practically eliminate its adjustment during the manufacturing process.

The installation of the required durations of the edges of the programming pulses consists in entering into the register 22 a code that determines the duration of the front of the programming pulses for the selected type of chip. The code from the register 22 provides the connection of the necessary capacitive blocks 39 through the switches 40 and the keys 38 to the inputs of amplifiers 6 (7.8) of power, which leads to an increase in the duration of the fronts of the signals taken from amplifiers 6, 7 and 8.

Main mode.

The operation in this mode consists of the following steps, which begin, after manual or automatic entry, from the external device, the information to be programmed into the computer memory.

1. Control the contents of the chip. The microcircuit to be programmed is installed in slot 34 and the control program that determines whether the microcircuit is programmed or not is started (if partially programmed, which addresses are free, if there are defective bits, what is their location). If there are defective bits, then an array of recorded information is searched for from a computer memory that contains matching information in these positions. If there is no such array from a limited set, then, depending on the algorithm put in, a new array will be introduced, or a programmable microcircuit will be considered unusable and should be replaced.

The control of the contents of the chip is implemented as follows.

According to the codes supplied to the control inputs 31, 32 and 33 of the device from the computer, the outputs of the pulse shapers are set to the voltage corresponding to the mode of reading information from the chip. In register 14, the code corresponding to the initial contents of the microcircuit is entered into register 16 — the code corresponding to the mode of reading information and the type of output of the programmable microcircuit (open collector or three states). According to the codes received from registers 14 and 16, key block 11 is switched to read mode and connected via the appropriate keys to | Circuit wired load resistors to the outputs of the microcircuits. In register 17, addresses are sequentially entered with the address codes of words to be read. The signals read from the microcircuit are fed to the inputs of the first group of control unit 12, where the levels of readable signals are compared with the reference ones from the source 15 of the reference voltages. The value of the reference voltage is low (corresponding to the standard value of the Log.O level) or high (corresponding to the standard value of the Log.1 level) is set by the corresponding register bits 14, which are fed to the inputs of the second group of the control unit 12. In block 12, the levels of the read signals are compared with the reference ones. At the output of block 12, a code appears whose sensory bits take an inverse value with respect to the code written to register 14. The verified codes of the read numbers through the amplifier 26 enter the computer, where they are further processed according to the described algorithm. After controlling the chip, the programming process begins.

2. Programming chips. In accordance with the selected chip type, the corresponding sequence of programming pulses should be formed. At the same time, the duration of the programming pulses, their duty cycle and number are programmed in the control computer. The operation of the device in this mode is as follows. From the computer in the register 16 is entered the code corresponding to the recording mode, whereby the key unit 11 switches from to the information recording mode. In register 17, the address code of the programmable word is entered, and in register 14, the code to be recorded in the microchip, codes corresponding to the voltage inputs that need to be supplied to the corresponding inputs of the chip are written to the buffer registers 35 of the first, second, and third pulse shapers. Then, using the control signals received from the computer in the sequence defined by the technical conditions, the time diagram of the chip programming, the codes from the buffer registers 35 of the corresponding pulse formers are rewritten into the intermediate registers 36, from where they arrive at the inputs of the corresponding DAC 37 at the output which is the voltage level corresponding to the incoming code. This voltage through the corresponding power amplifiers 6, 7 and 8 is fed to the programming inputs of the chip and the power input of the block 11. In accordance with the code entered in the register 14, the corresponding keys of the key block are triggered, through which the voltage from the output of the power amplifier 8 goes to the programmable Chips of a microcircuit. The front of the programming pulse is determined by the code entered in register 22. If necessary, create a certain technical conditions pulse shape (duration, duty cycle, shape and duration of the fronts) respectively change the codes in registers 35 and 36 of the corresponding drivers 1, 2 and 3 pulses and register 22. Addresses and bits that cannot be programmed are automatically detected in a computer and skipped during programming.

The required number of programming pulses and programming modes are set programmatically in a computer. In the case of a change in programming, the appearance of new microcircuits with a new programming mode by changing the program in the computer, it is easy to switch to another mode.

programming. The introduction of a D / A converter 37 into shapers of 1, 2, and 3 pulses allows to provide almost any desired shape and amplitude of programming pulses. This expands the functionality of the device and ensures its versatility.

3. Programming Control. After programming each word, the programming is monitored. For this purpose, power amplifiers work out the necessary voltage when reading. Register 16 records the code corresponding to the read mode and the type of outputs of the programmable chip. The codes of the read numbers arrive at the control unit 12, where, as in the case of checking the contents of the chip, the levels of the read signals are monitored.

The code of the read number through the amplifier 26 enters the computer, where it is analyzed. If there are errors, then the programming of the next word begins, if there is an error, then depending on the programming algorithm, a repeated programming mode (additional) is possible, or a decision is made to replace the chip as defective.

4. Functional control. After programming the entire array of numbers, the operation at high frequency is monitored. From the computer in register 16 is set the code corresponding to the read mode. Register 14 records the codes of the readout of numbers, register 17 receives address codes. The power amplifiers 6, 7, and 8 apply voltages corresponding to the read mode. The codes of the read numbers go to the control unit 12, where the levels of the read signals are monitored. From the output of block 12, through the amplifier 26, the codes of the read number are sent to a computer, where they can be further processed, namely, a bitwise comparison with the corresponding standards stored in the computer memory is made, or a checksum is calculated.

The proposed device is essentially an interface card and can be used in any organization having appropriate mini- and micro-computers. The device contains common and simple nodes, which greatly simplifies the device and does not have high requirements for customization.

Claims (1)

DEVICE FOR PROGRAMMING CHARACTERISTICS OF PERMANENT MEMORY, containing the first, second and third pulse shapers, the inputs of the first groups of which are connected to information buses, the inputs of the second groups are connected to control buses, the outputs of the first, second and third pulse shapers are connected respectively to the inputs of the first, second and third power amplifiers, the outputs of the first and second power amplifiers are the first and second control outputs of the device, respectively, the output of the third power amplifier is dinene with the power input of the key block, the outputs of which are connected to the inputs of the first group of the control block and are the numerical outputs of the device, the inputs of the second group of the control block are connected to the output -; the first register and the inputs of the first group of the key block, the inputs of the third group of the control block are connected to a source of reference voltages, the information inputs of the first, second and third registers are connected to information buses, and the control inputs are connected to control buses, the outputs of the second register are connected to the inputs of the second key block groups, the outputs of the third register are the address outputs of the device, characterized in that, in order to expand the scope of the device by increasing the class of programmable microcircuits, but comprises a first, second and third pulse edges conditioners, fourth and fifth registers of ry · _Q, the comparison unit, a synchronized 1S tion, transmitter amplifier, the receiver amplifier and the digital-to-analog converter IV, information WMOs | A fourth and fifth rows registers and | the outputs of the amplifier-receiver of the middle are connected with information buses, the outputs of the fourth register are connected to the information and control inputs of the pulse front shapers, the outputs of which are connected to the inputs of the corresponding power amplifiers, the outputs of the third pulse shaper are connected to the inputs of the third group of the key block, the control inputs of the fourth and the fifth register and the outputs of the synchronization block 1134964 are connected to the control buses, the outputs of the fifth register are connected to the inputs of the digital-to-analog converter, in the output of which is connected to the first input of the comparison unit, the second, third and fourth inputs of which are connected to the outputs of the respective power amplifiers, the outputs of the comparison unit and the outputs of the control unit are connected to the corresponding inputs of the amplifier-transmitter, the outputs of which are connected to the inputs of the first group of the synchronization unit and the inputs the amplifier-receiver, controlling the input of the amplifier-transmitter is connected to the control output of the synchronization unit, the inputs and outputs of the first, second and third groups of which are the control input E outputs the first, second and third groups of devices, respectively.