SU1120336A1 - Device for checking microprocessor system - Google Patents

Abstract

A MICROPROCESSOR SYSTEM CONTROL DEVICE, containing a comparison unit, consisting of three comparators and an OR element, a switching unit, a pulse shaper, the first and second information inputs of the comparator comparator units are pairwise connected and connected to the first, second and third buses of the monitored device data, respectively The gating inputs of the comparators of the comparison unit are connected to the corresponding outputs of the switching unit, and the outputs of the comparators of the comparison unit through the OR element are connected to the input ohm pulse generator, the output of which is connected to the test input of the switching unit and is the output of the device, characterized in that, in order to improve the reliability of the system by restoring, with single failures, a failure analysis block is inserted into it, which contains the first, second and third D-triggers of queries, the first, second, third and fourth elements of the NL, the first and second elements AND, the counting trigger, the element NOT, and the first inputs from the first to the third OR elements are connected to the outputs of the corresponding comparators block In comparison, the second inputs from the first to the third OR elements are connected to the output of the first element AND, and the outputs to the fault inputs of the corresponding request B-triggers, the clock inputs of which are connected to the output of the pulse former, the information inputs of the D-request triggers are connected to the single potential bus , and the outputs - with the corresponding inputs} of the fourth element OR, and with the corresponding information inputs of the switching unit, the output of the fourth element OR is connected to the counting input of the counting trigger and the first the second element, whose second input is connected to the output of the element NOT and the second input of the first element AND, and the output is the output of a device interrupt request, the output of the counting trigger is set to the input of the element HE, the fault input of the counting trigger and the first input of the first element And form respectively, a reset signal input and a device confirmation signal input.

Description

The invention relates to railway automatics systems, in particular, to devices for controlling vehicle control skinches (MPS). Known control device. (MPS) control, containing two channels, in which the controlled parameters are logically connected with the samocontrol circuit. The channel codes through the amplifiers control the control contactors, keeping them in the on position until f 1 is damaged. The closest to the invention to the technical essence is a device for monitoring an automatic locomotive signaling system, comprising a comparator selector of a ny block, informational inputs of which are connected to data buses, and one of the outputs - a synchronization input of a control pulse shaper and an interrupt unit of program 2. However, the known device reacts equally to short-term failures and to persistent failures, at the same time shutting down the system of the control object or implementing the recommended ation system. This results in reduced system reliability. The purpose of the invention is to increase the reliability of the system by restoring when single failures. This goal is achieved by the fact that the device for controlling the MPS, containing a comparison unit, consisting of three comparators and an OR element, a switching unit, a pulse shaper, the first and second information inputs of the comparator comparator units are pairwise connected and connected to the first, the second and third buses of the monitored data of the device, respectively, building the inputs of the comparators of the comparator unit are connected to the corresponding outputs of the switching unit, and the outputs of the comparators of the comparator unit through the OR with A pulse generator is connected with the pulse generator, the output of which is connected to the gate input of the switching unit and is the output of the device. A failure analysis block is inserted that contains the first, second and third D request triggers, the first, second, third AND elements, counting trigger, NO element, with the first inputs from the first to the third OR elements connected to the outputs of the respective comparators of the comparison unit, the second inputs from the first to the third OR elements connected to the output of the first AND element, outputs - with c-inputs of corresponding D-triggers of requests, clock inputs of which are connected to the output of the pulse generator, informational, inputs of D-triggering requests are connected to the potential potential bus, and outputs - to the corresponding inputs of the fourth OR element and with the corresponding information inputs of the switching unit , the output of the fourth element OR is connected to a countable counting trigger and the first input of the second element AND, the second input of which is connected to the output of the element NOT and the second input of the first element And vpsod is output interrupt request device, countable trigger output connected to the input of NOT, effluent countable trigger input and the first input of first AND .The inputs form respectively the reset signal and the input signal SRB acknowledgment device. FIG. 1 shows a functional diagram of the device; in fig. 2 algorithm for processing failures. The device contains a comparison unit 1, a switching unit 2, a pulse shaper 3, an analysis analysis block 4, comparators 5-7, element OR 8, elements AND 9-11, output 12, B-triggers 13-15 requests, elements OR 16- 19, the element And 20, the counting trigger 21, the element NOT 22, the element And 23, the output 24 of the interrupt request. The unit 1 includes three comparators 5-7, the outputs of which through the element OR 8 are connected, to the synchronization input of the driver 3 of control pulses. The block 2 of the commutations includes three elements And 9-11 first; the inputs of which are combined with the input of the failure analysis unit and connected to the output of the driver 3 control pulses. The analysis block 4 also includes three D-flip-flop 13-l5 interrupt requests, the counting inputs of which are connected to the output, the information inputs through the elements OR 16-18 with the outputs of comparators 5-7 of block 1 ,. and the outputs, respectively, with the second inputs of elements AND 11-13 of block 4 and the inputs of element OR 19. The output of element OR 19 is connected to the first element AND 20 and to the counting input of the fault counter 21, to the information input of which the Reset signal from the microcomputer is fed. The output of the counting flip-flop 21 through the element HE 22 is connected to the second input of the element AND 20 and to the first input of the element AND 23, to another input of which the microcomputer receives an interrupt confirmation signal, and the output is connected to the combined second inputs of the elements 16-18. The control device works as follows. The signals from the data buses from three microcomputers of the system are fed to the comparator. 5-7, where pairs are compared. To fix the bus conditions at a certain point in time, the driver of the control pulses 3 generates a strobe polling pulse supplied to the comparators 5-7 through the elements 9-11 of block 2 and to the counting inputs of the D triggers 13-15. If there are no errors in the MPS operation, the polling pulse passes through the comparators 5-7 and the element OR 8 to the synchronization input of the imaging unit 3, and at the outputs i) -triggers 13-15 of block 4 there is no interrupt signal. If an error occurs in one of the microcomputers, the polling pulse is absent at the output of the corresponding comparator, the corresponding B-trigger generates the Interrupt Request signal, which, through the IL 19 element, arrives at the trigger 21 input, which records +1, and through the AND element, the other input of which through the element NOT 22 receives a signal from the trigger output in the program interruption block. The IPM accepts this interrupt and proceeds to the failure routine. To ensure such processing, the entire microcomputer program is divided into separate sections. In the channel of each program section, a control point is formed, which is the initial data and information on the state of the microcomputer recorded in a certain area of the RAM at the time of its formation. As soon as a signal is received The interrupt request from the MPS control device, all three micro-computers restore their state, issues a Confirmation of Interruption signal, and repeats the program that has been knocked down. If the error is not detected during the passage of the retrenched section, the flip-flop 21 is reset and the control device returns to the initial state. If the error is detected again, the second 1 is written to the trigger 21 and the output of the trigger 21 blocks the reset of the state of the corresponding) interrupt trigger, which in turn records the corresponding AND elements of the switching unit 2. If, after reconfiguration, an error is detected, there is no signal at the output of the comparator selector unit that synchronizes the operation of the driver of control pulses, and the system stops. Thus, the proposed device allows to increase the accuracy of monitoring the MPS by processing failures. System reconfiguration in case of failures does not occur; therefore, it is not necessary to check localized micro computers for each failure, looking for a malfunction, as in the well-known, especially since the failure rate, as mentioned, is 2-3 times higher than the steady-state failure rate.

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Claims (1)

A DEVICE FOR MONITORING A MICROPROCESSOR SYSTEM, comprising a comparison unit, consisting of three comparators and an OR element, a switching unit, a pulse shaper, the first and second information inputs of the comparators of the comparison unit being paired and connected to the first, second and third buses of the device's data being monitored, respectively the inputs of the comparators of the comparison unit are connected to the corresponding outputs of the switching unit, and the outputs of the comparators of the comparison unit through an OR element are connected to the input of the forms pulse generator, the output of which is connected to the probing input of the switching unit and is the output of the device, characterized in that, in order to increase the reliability of the system by restoring, in case of single failures, a failure analysis unit is introduced into it, which contains the first, second and third D request triggers, first, second, third and fourth elements OR, first and second elements AND, counting trigger, element NOT, and the first inputs from the first to third OR elements connected to the outputs of the respective comparators of the comparison unit, the second inputs from the first to third OR elements are connected to the output of the first AND element, and the outputs to the dump inputs of the corresponding D-triggers of requests, the clock inputs of which are connected to the output of the pulse former, the information inputs of D-triggers of the request are connected to the unit potential bus, and the outputs are with the corresponding inputs of the Fourth OR element and with the corresponding information inputs of the switching unit, the output of the fourth OR element is connected to the counting input of the counting trigger and the first input of the second element and And, the second input of which is connected to the output of the element NOT and the second input of the first element And, and the output is the output of the request to interrupt the device, the output of the counting trigger is set to the input of the element NOT, the reset input of the counting trigger and the first input of the first AND element form the signal input, respectively reset and device failure confirmation signal input. 1120336 2