SU1120312A1 - Device for controlling information exchange - Google Patents

Abstract

A device for controlling information exchange, containing first, second and third D-flip-flops, the counting input of the first D-flip-flop is the first input of the device, allowing the input of the first D-flip-flop is connected to the bus of the logical unit, the counting input of the second D-flip-flop is the second input of the device, different so that, in order to increase the speed of information exchange by eliminating the uncertainty of the inclusion of D-flip-flops from two closely spaced clock signals. it contains the first, second, third and fourth elements AND, the element OR, the first input of the first element AND and the second input of the third element AND are the third input of the device, the output of the first element AND is connected to the input of the zero setting of the first) trigger, whose direct output connected to the first input of the second element I, the output of which is connected to the enable input of the second) trigger, the inverse output of which is connected to the second input of the second element I, the direct output of the second D-trigger connected to the second inputs of the first element I and ale the OR input and the enable input of the third P-flip-flop, the counting input (of which is connected to the output of the third element I, the first input of which is connected to the output of the element OR, the direct output of the third O-flip-flop is connected f. to the first input of the fourth element I, the second input of which The fourth input of the device, the output of the fourth element AND is connected to the terminal: A9 to the first input of the OR element and is the output of the device.

Description

The branch relates to computing equipment, in particular, to data input devices in a memory device, and can be used in the control unit of the data input device f memory device.

A device is known which serves to start a NCC unit from asynchronous pulses, which contains three flip-flops. It uses CC1 and CC2 that are shifted one relative to the other. The input non-synchronous signal is set to one of the triggers, which, with its output signal, synchronously with the CC2 coaxes another trigger, which, in turn, sets to 1 third trigger, generating the output pulse of the device in the next clock phase synchronously with the CC1. The role of the first of these triggers is to memorize the input signal until the appearance of the CC2 sync pulse nearest in time. Since the conditions for starting the second trigger, due to the non-synchronization of the first trigger with the sync pulse CC2, may be unstable, interference may occur at its output. They get rid of it by launching the third trigger with shifted CC2 pulses 1.

The closest to the invention in terms of the essential features is the device pulsed in computer M-10, containing the first, second and third triggers and the first, second, third and fourth elements I. The output of the second trigger is connected to the inputs of the third and fourth elements And jumpers on the switching field. The input signal, which is not synchronous with the synchronization circuits used in the device, is set to 1 first trigger at an arbitrary time. The second trigger in time is set to 1, the second trigger is set. The output of the second trigger is dropped to O, the first trigger is set, and the sync pulse (si) is allowed to be set to 1 of the third trigger. The first trigger in state O allows a reset on the next SI second trigger of the third trigger. As a result, a single-ended output signal is generated at the output of the device at each input signal, synchronous with SI N,

A disadvantage of the known device is the low rate of information exchange, due to the following. Since, in order to avoid memory overflow, each write cycle must correspond to one reading cycle, the write frequency (reading) of the memory limit is

one

Since the input signal 2T

sy

If the message accompanying the information recorded in the memory or being a read request appears at any time, it is not known in advance whether the write request (read) generated by the device can be satisfied in the same cycle or in the adjacent one. At the same time, if the first trigger is concluded simultaneously or almost simultaneously with the SI, which launches the second trigger, uncertainty arises: the second trigger may be activated in the same clock cycle, or in the next one. If it turns out that with the two following input signals with an interval of two clocks, almost coinciding in phase with the SI2, the second trigger from the first one turns on only through the clock, and from the second immediately, while the memory is occupied by the read access, The first information will be lost. In order for this not to happen, the follow-up period of the input signals must be equal to 2 Tr + d. The value of D must be greater than the uncertainty interval for triggering from two signals that are closely spaced in time. For example, for triggers of type 133 TM2, this interval is called preset time and is equal to 20 ns. Thus, the fundamental achievement of the limiting exchange rate of memory

is impossible.

The aim of the invention is to increase the speed of information exchange by eliminating the uncertainty of the inclusion of P-triggers from two closely aligned clock pulses.

The goal is achieved by the fact that the device for controlling the exchange of information containing the first, second and third D-triggers, the counting stroke of the first 33 Trigger is the first input of the device, allowing the input of the first 1) trigger to be connected to the bus of the logical unit, the counting input of the second) -trigger is the second input of the device, contains the first, second, third and fourth elements AND, the element OR, the first input of the first element AND and the second input of the third element AND are the third input of the device, the output of the first element AND is connected to One setting of the zero nepBoroD trigger, the output of which is directly connected to the first input of the second element, the output of which is connected to the enabling input of the second) trigger, the inverse output of which is connected to the second input of the second second element, and the direct output of the second D trigger, connected to the second inputs of the first element AND of the 1-SHI element and the enabling input of the third D-flip-flop, the counting input of which is connected to the output of the third element AND, the first input of which is connected to the output of the OR element, the direct output of the third) -rigger vomu fourth input element and the second input of which is the fourth input device, the fourth output element and connected to a first input of OR and is an output device. FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - time diagrams. The device contains the first element AND 1, the first O-trigger 2, the second element AND 3, the second D-trigger 4, the element OR 5, the third element AND 6, the third D-trigger 7, the fourth element And 8. All elements entering the device and triggers can be implemented on widespread chips of small and medium degree of integration. For example, microcircuits of type t33TM2 with synchronous inputs (enable input D and synchronization input C) can be used as triggers. At input C, the trigger is set from the positive front of the input signal to 1 or O, depending on the polarity of the signal of input D. A reset signal is sent to the input to O, the outputs and inputs, indicated by circles, are inverse. To record information received at an arbitrary point in time, it is necessary to generate a record request signal (PAD) by an external tracking information signal (BC) that satisfies two conditions: it must be synchronized with the synchronization frequency used by the storage device of the information input device, and Must not be the same as the read request from this charger. The device works as follows. In the initial state, all the triggers are set to O. The accompanying information of the aircraft, at the time of its appearance at the device input, sets its first front 2 to 1 with its positive front. Since the second input of the second element And 3 already has 1 coming from the inverse input of the second trigger 4, then the resolution appears at the C input of the trigger after the arrival of the aircraft, and the trigger 4 switches to 1 along the front of the nearest CI2 (Fig; 2), after which the first element 2 And 1 is reset to reset the first trigger 2 to CI1 . At the same time, the signal from the output of the second Tpiirrepa 4 through the element OR 5 forms the resolution at the third element. Ment 6 for setting in 1 of the third trigger 7 on the nearest SI1. The first trigger 2 is in state 1 for one SI1. If there is no FQ in this period, then due to the resolution at the second input of the element AND 8 from the FQ, at the output of this element in the same period, SI1 generates a PAD request. If in this period there is an FN signal, then the request is absent, the output of the OR 5 element is not resolved and the next SI1 does not change the state of trigger 7. This trigger continues to remain in state 1 another period SI1, allowing the request signal to be generated for a period later when there is no FST. The timing diagram (Fig. 2) shows only the working fronts of the signals BC, CI, CI2 and the situation that arises in the most critical case: the AC appears at such a moment when the 2 in 1 trigger is set up in close proximity to the CI2. In this case, there is no certainty: the trigger 4 may work from the nearest CI2, and maybe from the next. FIG. 2 solid worst case, when the line shows trigger 4 triggered from the next SI2, resetting trigger 2 is delayed by this until the next SI1, and the second triggering of trigger 4 due to a ban from its inverse. the output will now necessarily occur a period later. Thus, a gap of at least one period is provided between the trigger actuations from different aircraft. This 11203126 gap is necessary for cases of occurrence of the FST in the same period when trigger 4 from the first aircraft occurs, so that the information accompanied by this aircraft does not lose.

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Claims (1)

DEVICE FOR CONTROLLING INFORMATION EXCHANGE, containing the first, second and third © triggers, the counting input of the first D-trigger is the first input of the device, allowing the input of the first © trigger is connected to the logical unit bus, the counting input of the second © trigger is the second input of the device, characterized in that, in order to increase the speed of information exchange by eliminating the uncertainty of the inclusion of © triggers from two closely spaced clock signals, it contains the first, second, third and fourth elements of And, OR element, the first input of the first element AND and the second input of the third element AND are the third input of the device, the output of the first element And is connected to the zero setting input of the first © trigger, the direct output of which is connected to the first input of the second element AND, the output of which is connected to the enable input the second © trigger, the inverse output of which is connected to the second input of the second And element, the direct output of the second © trigger is connected to the second inputs of the first And element and the OR element and the enable input of the third © trigger, the counting input to is connected to the output of the third AND element, the first input of which is connected to the output of the OR element, the direct output of the third © trigger is connected to p: the first input of the fourth AND element, the second input of which is the fourth input of the device, the output of the fourth AND element is connected to the first input of the OR element and is the output of the device.