SU1117809A1 - Digital d.c.drive - Google Patents

Abstract

1. DIGITAL ELECTRIC DRIVE .CURRENT CURRENT, containing an electric motor with a pulse sensor and a rotational speed meter, connected to the output of a pulse-width converter, with an input connected to a pulse-width modulator connected to the outputs of the m most significant bits of the digital frequency controller, the first input of which It is connected with the output of the task unit, and the second with the output of the rotational speed meter, characterized in that, in order to improve the accuracy of controlling the rotational speed, a small accumulation unit is inserted into it n of bits, whose inputs are connected to the outputs of n LSBs of the digital frequency controller of the torus, and the output to the other input of the pulse width modulator. 2. The actuator according to claim 1, about tl and chsya. the fact that the accumulator of the least significant bits contains (L series-connected adder, n inputs of which form the inputs of the accumulator of the younger bits, the first delay element and the trigger, the output of which forms the output of the accumulator of the younger bits, and the second element is connected to the reset input of the trigger delays.

Description

f 11 The invention relates to electrical engineering and can be used in numerical control systems of direct current electric drives, in digital high-precision speed stabilization systems. A digital DC electric drive is known, which contains an electric motor connected to a transistor converter and equipped with a pulse shaft rotation angle sensor. The required rotational speed of the motor is set here in digital form using a microprocessor. At high rotational speed, the regulation is carried out by counting the number of pulses of the shaft angle of rotation sensor for a given measurement time, while at low frequency, by determining the period duration. The microprocessor is used to calculate the actual values of the parameters to be determined, to implement the control algorithms and generate signals, control lj The disadvantage of this electric drive is the low accuracy of the motor speed control. The closest to the invention to the technical essence is a digital DC motor containing a motor with a pulse sensor and a rotational speed meter, connected to the output of a pulse-width converter, with an input connected to a pulse-width modulator connected to the outputs of m higher-order There are additional digital frequency regulators, the first input of which is connected to the output of the reference block, and the second to the output of the speed meter 2j. A disadvantage of the known electric drive is also the low accuracy of rotational frequency control. The digital pulse-width modulator with double-sided modulation has an eighth input, which determines the length of the output word of the digital frequency controller, as well as the value of the quantization relative to the pulse length 1/256. The presence of quantization with a specified bit size of the output word of the digital frequency regulator inevitably leads to self-oscillations with an amplitude of at least one sample, which is 0.4% of the entire voltage control range of the electric motor. 2 In addition, the output word width in a known electric drive is rigidly related to the dynamic properties of a pulse-width converter (SHIP) and a digital frequency controller. The increase in the size, on the one hand, is limited by the speed of the microcircuits, on the other hand, the increase in the thermal loss of the switch when switching power switches in the SHIP. The aim of the invention is to improve the accuracy of speed control. The goal is achieved by the fact that a digital DC electric drive containing a motor with a pulse sensor and a rotational speed meter, is connected to the output of a pulse-width converter, with an input connected to a pulse-width modulator connected to the outputs of the most significant bits of a digital regulator frequency torus, the first input of which is connected to the output of the setpoint-. The second, with the output of the rotational speed meter, introduced an accumulator of lower bits, the inputs of which are connected to the outputs of the lower bits of the digital frequency controller, and the output to another input of the pulse-width modulator. The least significant bits accumulator contains a series-connected adder, the n inputs of which constitute the inputs of the least significant bits accumulator, the first delay element and the trigger, the KOTopioro input forms the output of the younger bits accumulator, and the second delay element is connected to the trigger input. FIG. 1 is a block diagram of a digital DC motor; in fig. 2 is a block diagram of the low order bit accumulation unit and the pulse width modulator. The digital DC motor contains a motor 1 with a pulse sensor 2 and a speed meter 3 connected to the output of a pulse-width converter 4 and connected to a pulse-width modulator 5 connected to the outputs of the higher bits of the digital regulator 6 frequency, the first input of which is connected to the task unit (not shown), and the second with the output of the meter 3 rotational speed. The low-order accumulation unit 7 is connected to the outputs of the lower-order bits of the digital frequency controller 6, and the output to another input of the pulse-width modulator 5. The accumulator 7 accumulator unit 7 has a series-connected adder 8, the inputs of which form the inputs the low-order accumulation unit 7, the first delay element 9 and the trigger 10, the output of which forms the output of the lower-order accumulation unit 7, and the second delay element T1 connected to the pulse-width bus is connected to the reset input of the trigger 10 for example, the register 12, whose inputs form the m inputs of a pulse-width modulator 5 connected in place with the counter 13 to the Start bus, while the outputs of the register 12. and the counter 13 are connected to the comparison unit 14, connected with logic element 2I-OR 15 and with D-trigger 16, connected to two logical elements AND 17 and 18, forming the output of pulse-width modulator 5, and to generator 19. Other inputs of logical elements And 17 and 18 are connected respectively with the register 12 directly and through a logical email NOT 20 item. The digital direct current drive operates as follows. Information on the speed reference code and the actual (actual) speed of the motor 1 is fed to the input of the digital frequency controller .6 (Fig. 1). Digital frequency controller 6 processes the received information and controls the control code as a bit. m + n bits, with m higher bits being fed to the inputs of a pulse-width modulator 5 (the wth discharge is under sign and n younger ones - to the inputs of block 7 at the top of the least significant bits. Information from block 7 of the younger ones bit enters the input latitude-imp street modulator 5 through K-periods (cycles), where the number K determines c from the expression K-M 2, where M is the number specified at the inputs of accumulator 7 of the least significant bits, an-.

the number of its bits (inputs). This happens as follows. The code inputs of the register 12 (Fig. 2) and the adder 8 are supplied with code information in the form of a parallel code of digit t + n bits, with n bits (minor) being fed to the inputs j) a 8, and m bits (first) - to the I inputs of the register 12, the mth bit of which is clicked under the sign. Then the Start command is given, by which the high part of the code is written into the register 12, the younger part is added to the contents of the adder 8, the counter 13 is set to the state O ( trigger 10 of the readout memory is in the state O) and with the aid of the logic element 2I-ISH 15 (to the inputs of Then, the Start command and the strobe from the second output of the generator 19 are received. A write pulse is generated at the input C of the D flip-flop 16. The Start command comes from the digital controller 6, whose role is played by the micro-computer. At the time of recording the code information in the register 12 and the arrival of the counting pulses from the first output of the generator 19 to the first input of the counter 13 at the first output of the comparison unit 14, a signal is generated (as a non-comparison of the codes from the register 12 and the counter 13), for example, 1, a high level arrives at the D input of the D flip-flop 16. At the same time, a write pulse is generated from the output of the 2I-OR 15 logic element on the Start command and the strobe coming from the second output of the generator 19. Thus, the D-flip-flop 16 records informationbeginning of the time interval. This information (in example 1) from the output of the D-trigger 16 goes to the second inputs of logic gates AND 17 and 18. Depending on the state of the sign bit of register 12, the logic element operates. Both 17 (or 18) and a signal appears at its output. At the moment of comparing the code recorded in register 12 with the code coming from counter 13, comparison unit 14 generates at the first output a signal (for a given case O), which is fed to the input D of the D-flip-flop 16, and at the second output a signal that , the passage through logic 51 element 2I-OR 15, simultaneously with the strobe coming from the second output of generator 19, generates a pulse record for input C of D-flip-flop 16. Thus, information about the end of the time interval is recorded at D-flip-flop 16 . This information as a prohibition (in the example O) from the output of the D-flip-flop 16 goes to the second inputs of the logical elements I 17 and 1 and removes the signal at their outputs. Thus, at the output, a time interval T is formed, corresponding to the code recorded in register 12 (the upper part of the input code) and defined by the expression where T is the pulse period of the generator 19; N is the number corresponding to the oldest m bits of the input pulse width MO code. The blower 5. The arrival of the following Start command (follows with a constant clock frequency, digital frequency controller 6 frequency) causes a repetition of the cycle of formation of the time interval T-. At the same time, the contents of the adder 8 accumulates. After K periods (cycles) of modulation, a signal appears at the output of adder 8, which, after a period of time determined by delay elements 9, sets trigger 10 of the readout memory to state 1. Entering the following Start command sets counter 13 to 1 (all bits of the counter are set to the state. Through the time interval Un (less than Lj) determined by the delay element 11, the trigger 10 of the readout memory is reset to the initial state O and prepared for storing the next overflow signal of the adder 8. So Thus, to fill the counter 13 to coincide with the code recorded in register 12 (corresponding to the most significant bits of digital frequency controller 6), an additional period of frequency of generator 19 is required, and a time interval T is formed at the output of pulse-width modulator 5, Thus, a pulse-width modulated signal of a pulse-width modulator 5 with a pulse duration Tj is received at the input of the pulse-width converter 4, which is a nine-power amplifier, with a pulse duration Tj, defined by. the leading part of the input code and the state of trigger 10 of the readout memory. The zero state of the trigger 10 is the memory of the readout T T N. With a single state of the trigger 10 of the memory of the readout, one pulse of duration occurs: (N + 1) TjjN-bT (, T, -t-To, where TD is the period of the pulse generator 19; N is the number recorded in the higher bits of the input code. Thus, the signal from the pulse-width modulator 5 can be represented as the sum of two signals with pulses of duration T following with a frequency of 1 1 const and single pulses of duration T with a variable frequency depending on the number of times written in terms of the number of rows, the rows f - r - 2M t C in the output of the pulse-width modulator 5 signal is fed to the pulse-width converter 4, the voltage of which controls the electric motor 1. The average voltage on the bark of the engine 1 is the sum of two voltages with average values of T ". N and" .. TN Ua M 2. Full ffenation for the average value of the voltage on the engine is, U, 2-SN + | n | ;;, :() Thus, the main component of the voltage U is formed by the high-frequency signal of the pulse modulator 5, providing tolerance / 1

These are the frequency fluctuations of the engine 1, according to which the rank of the highest m is chosen.

A precise adjustment of the rotational speed of the engine 1 is made by the voltage Uj, the average value of which is formed by short pulses with a pulse duration equal to the pulse period of a high frequency generator 19, which follow a lower frequency than the main signal.

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The information about the frequency of rotation of the engine 1 is recorded by the pulse sensor 2 and is processed from the epithels by 3 rotational frequencies, from the output of which information is fed to the digital frequency regulator 6.

Thus, the introduction of the accumulator of the least significant bits allows to increase the accuracy of the operation of the digital to electric drive of direct current.

without a significant increase in the pulsations of the instantaneous frequency of rotation of the engine.

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Claims (2)

1. A DC digital electric drive containing an electric motor with a pulse sensor and a speed meter, connected to the output of a pulse-width converter, connected to a pulse-width modulator connected to the outputs m of the upper bits of the digital frequency controller, the first input of which is connected with the output of the reference unit, and the second with the output of the speed meter, which is connected with the fact that, in order to improve the accuracy of controlling the speed of rotation, an accumulation block of younger p stages, the inputs of which are connected to the outputs η of the least significant bits of the digital frequency controller, and the output to another input of a pulse-width modulator. 2. The drive according to claim 1, characterized in that the low-order accumulation unit contains a series-connected adder, η of the inputs of which form the inputs of the low-order accumulation unit, the first delay element and a trigger, the output of which forms the output of the low-order accumulation unit, and to the reset input The trigger is connected to the second delay element. SU., „1117809